in the attached project an eDMA Major Loop gets triggered after enabling peripheral requests in eDMA channel 0 despite no PIT trigger events occurred and therefore the first data is lost.
The example simply copies the first 10 elements of sourceBuffer
to the first 10 elements of destinationBuffer after a PIT CH0
trigger (every 0.5 seconds) and fires an interrupt when finished.
Every ISR run increments a counter.
After the interrupt fired the buffers and the counter are printed to the
DEBUG console. Afterwards the counter gets reset to 0 and the source buffer
gets initialized with new data.
The buffers are double the size in order to check correct eDMA settings.
1. Initial setting as attached to this post
The MCUXpresso Config Tool Peripheral setting for eDMA CH0 request is set
to DMAMUX always on.
Because of this setting the first eDMA Major Loop
transfer will be triggered after the function call
in peripherals.c line 181 despite the HRS register of DMA0
not showing any hardware request. If you take a look at the TCD0_SADDR and
TCD0_DADDR you see that the set values are correct before executing above
function. After executing and enabling the channel request SADDR and
DADDR get incremented by one and now show to an incorrect address.
The first expected data of 0x00 will not be transfered after the PIT channel
is started in main. Every following Transfer works as expected.
2. Now change the MCUXpresso Config Tool Peripheral setting for eDMA CH0
request to DMAMUX disable and update the code. The DMAMUX will be enabled
before the PIT is started in main.
This way everything works as expected. The first data 0x00 gets transfered
The init function is not following the Initialization chapter for DMAMUX of RT1020 Reference Manual.
Is the DMAMUX/eDMA/PIT initialization order incorrect in Config Tools v7?
Why is a eDMA transfer triggered in 1 if we enable DMAMUX first?