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State of GPIO when i.MX7ULP is in VLLS mode

Question asked by ko-hey on Feb 24, 2020
Latest reply on Feb 25, 2020 by terry_lr

Hi all,

 

I have a question about state of GPIO when it's in VLLS mode.

According to the Table 27-8 of reference manual, RGPIO2P0 is power gated.

So I guess that it can't keep the state before entering VLLS mode.

 

Am I correct ?

 

Ko-hey

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