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ddr clock frequency

Question asked by Jakob Thomsen on Feb 21, 2020
Latest reply on Mar 12, 2020 by jakob thomsen


We have a custom board based on imx7d with DDR2 RAM. The current DDR2 RAM is running at 533 MHz, but the DDR2 only support up to 400MHz.

In the bootloader we select clock source use DRAM_ALT_CLK_ROOT and SYS_PLL_PFD0 and hereby the DDR phy clock is running at 392Mhz.

When the Linux kernel boot, the DRAM clock dead after statement clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0) in source file clk-imx7d.c.

Looking forward for inputs.