I am running the DDR2 batch simulation. Before starting the simulation, I have developed the memory controller timing model (MCU model: MK61FN1M0VMJ15) through DDR2 controller timing model wizard. To develop the timing model, I need to get the setup time (tDS) and hold time (tDH) during the read operation.
By refering to the datasheet of K61 MCU (Document Number: K61P256M150SF3) page 44. The datasheet only mention about the tQS and tQH during DDR write operation but didnt mention about the tDS and tDH for read operation. Do you guys know where to get this information ?
When I read through the app note (AN10706) which is the document on developing the timing model for Hyperlynx simulation, I saw some of the memory controllers will delay the DQS by having 90 degree phase shift in their internal register. Not sure will the memory controller internal register will do the same thing during read operation? If yes, the datasheet didnt mention about the DQS skew during read operation in internal register. Do you guys know about this and where to get this information?
The following are the configuration for the memory controller,
DDR class: DDR2
Clock rate: 150 MHz