I use the spi for getting a data like upper picture.
I sent two tx bytes, and get a data.
in this case first loop, I can get a right data in variable receive, but second loop i can't get a right data.
Also, I check the register rx fifo overflow bit is always set after every LSSPI_DRV_MasterTransferBlocking
so i want to modify like this for testing. in this case i always can get a right data.
Could you please share a test project with the the LPSPI driver configuration?
Can you just connect MOSI - MISO to test the driver?
Do you monitor the bus with a logic analyzer?
Thanks,
BR, Daniel