the LPSPI Transmit Data Register TDR is built so that it zero-extends 8 and 16 bit writes
We want to fill the FIFO with DMA transfers. In case I have 5 bytes of data and a Framesize of 5 * 8 = 40 to send I will have one 4 byte DMA transfer and one 1 byte DMA transfer.
The last DMA transfer will only write 8 bit to the register therefore the bits 8 to 31 will be zero.
- If the LPSPI module is set to MSB first will it send the zero data bits 24 to 31 instead of my expecet data?
- If yes is it possible to write to bits 24 to 31 in TDR with DMA and will the lower bits automatically be 0 too?
- Because of the limitation of DMA to 1,2 and 4 byte transfers it is not possible to send e.g. 3 bytes because I would have to write first 2 bytes to TDR (which will result in 2 zero bytes and 2 data bytes in TX FIFO) and then 1 byte (3 zero bytes in FIFO) which will result in at least 2 unwanted zero-bytes sent out through SPI right?