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Bug in lpspi driver?

Question asked by Stefan Mitterhauser on Feb 13, 2020
Latest reply on Feb 17, 2020 by Stefan Mitterhauser

Hello,

 

I was just testing the LPSPI driver and realized that the clock cycles in register LPSPI1>SCKPCS, PCSSCK and DBT get set wrong. I think there is a bug in the function LPSPI_MasterSetDelayTimes of the fsl_lpspi.c SDK driver.

 

I am using SDK_2.7.0_EVK-MIMXRT1020_FreeRTOS with fsl_lpspi driver version

#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))

 

If you look at the function the variable realDelay is of type uint32_t. On line 658 of fsl_lpspi.c the variable gets set to

realDelay = 1000000000U;

which is roughly maximum value of uint32_t divided by four and on line 659 realDelay gets multiplied by the scaler plus some offset

realDelay *= (scaler + 1U + additionalScaler);

The scaler will start with 0 and go up to 255 which will result in too large data.

 

If I change the data type of realDelay (and I think the same problem is true for bestDelay) to uint64_t I get the correct result. Is this enough or do I have to change anything else?

 

Kind regards,

Stefan

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