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Verification models for free I3C slave IP

Question asked by Stephan Dolezal on Feb 12, 2020
Latest reply on Apr 9, 2020 by ethan cheng

I'm using the free NXP I3C slave IP (https://github.com/NXP/i3c-slave-design) and found it very helpful to write a minimalistic I3C master simulation model for testing the reaction of the I3C slave to understand how it works in detail.

 

Is there an official I3C master simulation model for verifying my design? Or are there any hardware devices capable of serving as an I3C master for verification?

 

Thanks and best regards,

Stephan

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