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SDRAM Controller Reg SDMR latch data question

Question asked by Zachary Wilcox on Feb 10, 2020
Latest reply on Feb 22, 2020 by TomE

I'm working with the MCF5485 and setting up DDR DRAM.

I'm attempting to set the SDMR register.  It appears it doesn't latch the data unless I also set the command bit.

Here's an arbitrary example where the data doesn't latch:


uint32_t* sdrm = (uint32_t*) SDMR_ADDRESS;

uint32_t  bank_addr = 0x40000000;

uint32_t address = 0x58C0000;

uint32_t command = 0x10000;

*sdrm = bank_addr ;
*sdrm |= address ;
*sdrm |= command 



sdrm = bank_addr  | address ;
*sdrm |= command 


However, the following latches the data.

*sdrm = bank_addr | address | command  ; 



I don't see anything in the Reference Manual stating this bit needs to be set to latch the data.  

Am I doing something wrong in the first two examples, or does the command bit need to be set to latch the address and bank address.