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How should I understand the IOMUX?

Question asked by Yan Ding on Feb 9, 2020
Latest reply on Feb 11, 2020 by gusarambula



I am new in embedded hardware, currently working with 7 (MCIMX7U5DVK07SC). After reading the "i.MX 7ULP Applications Processor Reference Manual" and the EVK, I am still confused on the IOMUX function. So far, my understanding is that PTA~PTF ports are function limited GPIOs. The developers need to define the port group (A to F) among Alternative 0 ~ 14.


However, when I look at ALT1: PTA0 is PTA0 ... PTF19 is PTF19. Is this means they can be any low speed bus? I can get 30 I2C bus if necessary? I can get 20 SPI bus if I need? Understand they belongs to different Core.


I am working on PCB layout. Due to the board size and siganl layer count reason, I wish to understand the iomux to see how flexible I can define each pin. So that the traces won't be tangled and makes the layout easier.