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iMX6 GIC Documentation

Question asked by Ken Green on Feb 5, 2020
Latest reply on Feb 6, 2020 by Ken Green

I would like some verification on my understanding of exception handling in the Cortex A (specifically the iMX6 A9) architecture. It appears that exceptions can be divided into two categories. The first group (reset, undef, svc, prefetch, abort, irq, and firq) are part of every ARM architecture, and in the Cortex A they can be located starting at either 0x00000000, 0xFFFF0000 depending on the V bit in the SCTLR. It appears most OS's set the V bit so the vectors are in high memory. For instance, location 0xFFFF0004 holds an instruction such that when this exception occurs, the instruction at that address is executed. The most common instruction used is LDR  PC, #offset.


All other interrupts appear to run through the GIC. There is a little discussion in section 12.2 of the ARM Cortex A Programmer's Guide, but nothing on how to program it (registers, bits in registers, etc.). This is what I'm trying to find. Where is the documentation for the GIC? Nothing in the RM or the ARM Cortex A9 Technical Reference Manual. I can dig a few things out of the BSP code, but I would still like some documentation.


For instance, if the address of the reset, undef, … vector table is fixed at 0x0000_0000 or 0xFFFF_0000 (and the core knows where it is by the V bit), what is loaded into the VBAR and how is the value determined?


Thanks for your help.