For an audio application, I need to configure the SAI peripherals and the GPT so that the peripheral clock frequency is exactly the same - for example 12.288 MHz.
I was unable to obtain this result. The best solution I found was:
- configure PLL2 as 24*(22+85/161) and supply it to the core and the GPT (divided by 44)
- configure PLL4 as 24*(32+92/119) and supply it to SAI ports (divided by 64)
These frequency are close, but not the same, and this may create artifacts in the audio signal.
Another possible solution could be to output peripheral clock root to CLKO1 and feed it back to CCM_CLK. Honestly I don't like it, because so far we have had various robustness problems with CCM.
A third, and possible best solution is to use a 24.576 MHz crystal instead than 24 MHz.
This is not explicitly permitted on the datasheet, but it is not even explicitly forbidden.
So, the question is: can I use a 24.576 MHz crystal as main clock for the RT1051? Should I expect any drawbacks?