LPC55S69 : Special GPIO pins

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

LPC55S69 : Special GPIO pins

525 Views
EugeneHiihtaja
Senior Contributor I

Hi !

In DS chapter 6.1 is written like this:

"

All pins have all pull-ups, pull-downs, and inputs turned off at reset except PIO0_2,
PIO0_5, PIO0_11, PIO0_12, PIO0_13 and PIO0_14 pins. This prevents power loss
through pins prior to software configuration. Due to special pin functions, some pins have
a different reset configuration. PIO0_5 and PIO0_12 pins have internal pull-up enabled by
default, and PIO0_2 and PIO0_11 have internal pull-down enabled by default. PIO0_13
and PIO0_14 are true open drain pins. Refer to pin description table for default reset
configuration.

"

Can I interpret this like this :

- under Reset those pins have Z-state  or for example PIO0_5 keep PU is even under Reset

- after Reset ( At the end of Reset ) there are special configuration applied

- by SW I can apply any other configuration later on. And not exists any limitations of any pin what configuration can be set. And everything is specified in Table 3 of DS.

Regards,

Eugene

Labels (1)
0 Kudos
1 Reply

475 Views
ZhangJennie
NXP TechSupport
NXP TechSupport

Eugene,

Yes, your understanding is right.


Have a great day,
Jun Zhang

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 Kudos