I am working on T2080 Custom board on which PCIe is connected to the upstream port of IDT PCIe switch (89PES4T4)and one of the downstream ports of the switch is connectd to Xilinx V7 FPGA (endpoint)
In the vxworks I have assigned 512MB of size to "memIo32Size" and FPGA has assigned 512MB of size to BAR0 address.
When pciHeaderShow is executed for FPGA, It shows wrong address which is not mapped to my "memIo32Addr"
But, when in vxworks if 512MB of size is assigned to "memIo32Size" and FPGA assigns 256MB of size to BAR0 address, address gets populated properly in pciHeaderShow
Why isn't the address not populated properly if RootComplex and Endpoint pcie memory size is equal