I2S output with I.MX6 Dual Lite

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I2S output with I.MX6 Dual Lite

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yuji_fuseki
Contributor II

Hi, 

We started our new application design with I.MX6 dual lite.

And, we plan to use DAC(, or DAMP) as slave device by providing I2S(LRCK, SCK, DATA) with MCK from I.MX6.

I found explanation about I2S at page.5077 on reference manual(i.MX 6Solo/6DualLite Applications Processor Reference Manual).

pastedImage_1.png

But, i don't understand how I.MX6 can output MCK that is synchronized with I2S signals.

please give your strong support.

Best regards,

yuji

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yuji_fuseki
Contributor II

Hi Igor

OK, i create new thread.

br,

yuji

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yuji_fuseki
Contributor II

Hi, Igor

Thanks for your explanation.

so, i understand that oversampling clock can be obtained from SRCK when that is unused to set SCR register bit15,SYS_CLK_EN.

And, I get further questions as below

 1) Each SSIx(x=1,2,3) is included STCK/STFS/SRCK/SRFS/STXD/SRXD signal lines?

 2) Each SSIx(x=1,2,3) are connected to internal port 1/2/7 of AUDMUX. Is my understanding correct?

 3) we can set port to port connection inside AUDMUX?(default configuration is below figure)

 pastedImage_8.png

 4) Each signals on external ports is connected SoC pad as Table 16-1?

Best regards,

yuji

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igorpadykov
NXP Employee
NXP Employee

Hi Yuji 

for new questions please create new thread.

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Yuji 

probably by "MCK" you means "oversampling clock", it is described in

sect.61.8.4 SSI Clocking i.MX 6Solo/6DualLite Applications Processor Reference Manual :

pastedImage_1.jpg

detailed clocking scheme can be found in Figure 61-22. SSI Transmit Clock Generator Block Diagram

Best regards
igor
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