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How to use PLL to generate precise clock frequency, with Linux, devicetree?

Question asked by Nicolai Christensen on Jan 30, 2020
Latest reply on Jan 30, 2020 by igorpadykov

Hello, I am creating a camera driver for IMX296 for the i.MX 8 MQ. I am struggling with generating the appropriate clock signal for the image sensor, which is either 37.125, 74.25 or 54 MHz.

 

I base my devicetree on the ov5640, and the devicetree for the imx296 looks like this:

  imx296_mipi: imx296_mipi@1a {
    compatible = "sony,imx296_mipi";
    reg = <0x1a>;
    status = "okay";

    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_csi1>;

    clocks = <&clk IMX8MQ_CLK_CLKO1_DIV>;
    clock-names = "csi_mclk";
    assigned-clocks = <&clk IMX8MQ_CLK_CLKO1_SRC>, <&clk IMX8MQ_CLK_CLKO1_DIV>;
    assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_200M>;
    assigned-clock-rates = <0>, <54000000>;

    csi_id = <0>;

    rst-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;

    mclk = <54000000>;
    mclk_source = <0>;
    port {
      ov5640_mipi1_ep: endpoint {
        remote-endpoint = <&mipi1_sensor_ep>;
      };
    };
  };

 

I try an ask for 54MHz, but the output become 50MHz which indicates that the clock divider used here is rounded to nearest integer, 4.

Is it possible to increase the accuracy of the PLL here, so that I can get these above mentioned frequencies?

I have tried to change assigned-clock-parents to <&clk IMX8MQ_SYS1_PLL_266M> which should be able to get close enough to 54MHz, dividing by 5, but this results in an error: "clk: failed to reparent clko1_div to sys1_pll_266m: -22".

What can I do to achieve the above mentioned frequencies?

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