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CK_FTx_DCC bit value of MMDCn_MPDCCR register

Question asked by Takayuki Ishii on Jan 28, 2020
Latest reply on Feb 27, 2020 by Takayuki Ishii

Hello community,

 

From rev.1 to rev.2 of Reference manual of i.MX6DP/QP, it was changed CK_FT0_DCC=100 bit setting

from "100 51.5% low 48.5% high" to "Reserved".

 

But Engineering Bulletin EB828(MMDC & NoC Configuration for Optimal DDR3 Performance on the i.MX 6DualPlus/6QuadPlus) not changed yet.

And Table 3.of EB828, it say that CK_FT0_DCC=100 setting is a recommended settings.

 

Q.1) Does it have an update of recommended setting of each CK_FTx_DCC?

Q.2) If CK_FTx_DCC=100 setting used, what happen? no effect 50%duty cycle default value?

       or it must change some other setting?

 

Best regards,

Ishii.

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