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Question for LPC11U68JBD100 SPI data transfer

Question asked by Tadaki Maekawa on Jan 23, 2020
Latest reply on Feb 3, 2020 by Tadaki Maekawa

CPU part number : LPC11U68JBD100

 

I am designing  LPC11U68JBD100 firmware.

I want to SPI transfer with A/D converter.

I use SPI0 port. CPU is master. the A/D converter is slave.

the A/D converter's data frame is 32bit per frame.

So, if SSEL (slave select) is deasserted during 32 bit data transfer, the A/D converter ignores the transferred data. 

So, I think 32 bit data transfer using continuous back-to-back transmissions without deassertion of the slave select.

 

Is there good way to transmit 32bit data from SPI0 port without deassertion of the slave select(SSEL) during 32 bit serial transmission?

 

Or, Is it possible to transfer the 32bit data with following way?

The way thinking currently is next:

  main register setting : CPOL = 0, CPHA = 1, DSS = 7(8bit transfer), MS = 0.

  Process:

   (1) Wait until TFE = 1 ( to output unnecessary data from transmission FIFO ).

   (2) Read the DR( data register) until RNE = 0 ( to output unnecessary data from receiver FIFO ).

   (3) SSE = 0 (to disable SPI transfer)

   (4)Write only 4 byte data into the transmission FIFO through DR ( 8bit * 4 = 32).

   (5) SSE = 1 (to enable SPI transfer)

   (6)Wait until BSY=0 ( to wait until SPI transfer is done) .

 

The register neme, signal neme used here is wrriten in UM10732 (LPC11U6x/E6x User Munual).

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