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iMX8QM DDR Configuration

Question asked by Stan Bertrand on Jan 21, 2020
Latest reply on Feb 17, 2020 by Stan Bertrand

Hi,

 

I would like to understand how to configure DDR for iMX8QM system.

Our board has 8Go of DDR4 which is more than the iMX8QM MEK board.

 

How to configure the system to indicate additional RAM to initialize ?

How is the DDR configured ?

There are 2 channels, are they configured in interleaved mode ?

How the channel mapped to the memory region ?

 

The SCFW porting kit has a number of tests that can be run. Some are relevant to DDR.

I am able to run the DDR and DRC test on iMX8QM MEK but the DDR stress test fails :

*** DDR Stress SC Test

Power up DRC 0
Power up DRC 1
Allocate memory
Init DDRC
board_init_ddr(1)
DDR frequency = 1596000000
board_init_ddr(0)
DDR frequency = 1596000000
Current DDR Clock rate:
- DRC controller0: 798000000Hz, -DDR0 PHY: 1596000000Hz
- DRC controller1: 798000000Hz, -DDR1 PHY: 1596000000Hz
The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value

Enter desired START freq in MHz and in 50MHz increments, then hit enter.

For example, for 1GHz, enter 1000, for 850MHz, enter 850.
1596
The freq you entered was: 1596 MHz

Enter desired END freq in MHz and in 50MHz increments, then hit enter.
Make sure this is equal to or greater than start freq
1596
The freq you entered was: 1596 MHz

Do you want to run DDR Stress Test for simple loop or infintely (till failure)?
Type '0' for simple loop. Type '1' for infinte test
0

----------------------------
DDR freq passed into function * 1000000: 1596000000

** pm_clock_enable error!, err 6
**Error occurred when trying to set DDR freq, re-start test

DDR Stress test ended due to detected data failure

 

Regards,
Stan

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