AnsweredAssumed Answered

About DDR_PHY_CMD_DESKEW_CONx

Question asked by goto11@wantsinc.jp on Jan 16, 2020
Latest reply on Jan 16, 2020 by Yuri Muhin

Hello,Community

 

I have two main questions.

1.There are the following four CMD DESKEW Control Registers in the i.MX 7Dual Applications Processor Reference Manual.
Is it a register that simply delays the output time?

 

DDR_PHY_CMD_DESKEW_CON0 ・ ・ ・ CA
DDR_PHY_CMD_DESKEW_CON1 ・ ・ ・ CA
DDR_PHY_CMD_DESKEW_CON2 ・ ・ ・ CS, CK, CA
DDR_PHY_CMD_DESKEW_CON3 ・ ・ ・ CS, CKE
DDR_PHY_CMD_DESKEW_CON4 ・ ・ ・ RST


2."https://community.nxp.com/message/879239" has the following description.
Can it be applied to all the above signals?

 

 

One delay value in this register is ~ 16.3 picoseconds
The register field values of 0x00-0x08 add no delay.
For this, 0x08 is effectively the zero starting point.Every setting above 0x08 adds one tFS delay.For example, a value of 0x12 adds 10 * tFS or 163 picoseconds of delay.

 

best regards

Goto

Outcomes