[LS1046A EP]:how to enable all six BARs as 32bit memory?

[zy_mooncity]

Dear folks,

In my scenario, there are two identical LS1046A boards connected. One acts as RC and the other acts EP. The two boards communicates through PCIe bus. All six BARs in the EP should be configured as 32bit memory so that the RC can access six different DDR region in the EP. Related fields in the RCW are configured correctly. 

On the EP board, I configured BAR0~BAR5 with all 0 (32bit non-preferable memory), and BAR0_MASK to BAR5_MASK with 0xFFFF (64K bytes). Inbound windows registers all also configured. see below:

BAR0:0x00000000 BAR0_MASK:0x0000ffff
VIEWPORT:0x80000000  LWR_TGT:0xfb000000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000000

BAR1:0x00000000 BAR1_MASK:0x0000ffff
VIEWPORT:0x80000001 LWR_TGT:0xfb010000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000100

BAR2:0x00000000 BAR2_MASK:0x0000ffff
VIEWPORT:0x80000002 LWR_TGT:0xfb020000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000200

BAR3:0x00000000 BAR3_MASK:0x0000ffff
VIEWPORT:0x80000003 LWR_TGT:0xfb030000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000300

BAR4:0x00000000 BAR4_MASK:0x0000ffff
VIEWPORT:0x80000001 LWR_TGT:0xfb040000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000400

BAR5:0x00000000 BAR5_MASK:0x0000ffff
VIEWPORT:0x80000005 LWR_TGT:0xfb050000 UPPER_TGT:0x00000000 RC1:0x00000000 RC2:0xc0000500

On the RC board, a outbound window is configured with 256M bytes to cover all the space configured in inbound windows. BAR0, BAR1, BAR2 and BAR4 can be read back with 64K bytes size, but BAR3 and BAR5 are read back with zero. Seems there is something wrong with BAR3 and BAR5.

BAR0, BAR1 and BAR2 work as expected (the RC can access the EP's DDR regions through BAR0, BAR1 and BAR2),

BAR4 does not work, read on BAR4 space always return 0xFFFF_FFFF.

My questions are:

1.  Can BAR3 and BAR5 can work individually?
2.  how can I enable all six BARs in EP as 32bit non-preferable memory individually?

Thanks in advance!

Regards

Yun

[zy_mooncity]

Thanks ufedor. So I have to disable BAR3 and BAR5 to ensure BAR2 and BAR4 can work as 32bit memory.

[ufedor · Accepted solution]

1) This is not possible - refer to the QorIQ LS1046A Reference Manual, 

25.4.2.13 PCI Express Base Address Register 2 (BAR2) stating:

"Together, base address register 2 (BAR2) and base address register 3 (BAR3) define a 64-bit inbound memory window. BAR2 defines the lower portion of the memory window; BAR3 defines the upper portion of the memory window."

25.4.2.21 PCI Express Base Address Register 4 (BAR4) stating:

"Together, base address register 4 (BAR4) and base address register 5 (BAR5) define a 64-bit inbound memory window. BAR4 defines the lower portion of the memory window; BAR5 defines the upper portion of the memory window."