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I2C-bus Status Register Descriptions

Question asked by Andrew Stephen on Jan 15, 2020
Latest reply on Jan 17, 2020 by Andrew Stephen

I am working with the MSP430FR2311 that has the SC18IM700 chip. I was writing tests for I2C master and slave communication between two of the same board. One is programmed as a master and the other as a slave. I was getting unexpected behavior when trying to test the I2CSTAT register values. Specifically the I2C_NACK_ON_DATA as seen below.

When sending a write command to the chip and receiving a nack after the address is sent it is being registered as a I2C_NACK_ON_DATA. I would think this should be considered a I2C_NACK_ON_ADDRESS instead. Is my assumption correct? I wasn't able to find proper documentation explaining when these different statuses are supposed to be set. If you could provide a better description of each status or link me to somewhere that describes this that would be best.

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