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Temperature measurement with ADC

Question asked by prashantdev on Jan 15, 2020
Latest reply on Jan 28, 2020 by Alexis Andalon

I am using MK61FN1M0VMJ12 microcontroller. I am trying to read it's temperature with built in sensor with ADC CH 26.  But I get constant reading of 64875(ADC0_RA) in differential and value 64 when in single ended mode. Same behavior is seen on CH 30. Same piece of code I tested on my K60 Tower Kit and it is working there properly. Can u please tell me what I'm doing wrong. Here is the initialization code:

void init_adc(){

tADC_Config Master_Adc_Config;
disable_irq(ADC0_irq_no) ;   // not ready for this interrupt yet. Plug vector first.
disable_irq(72) ;    // not ready for this interrupt yet. Plug vector first.
  SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK );
  SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ;
// Configure System Integration Module for defaults as far as ADC
  SIM_SOPT7 &= ~(SIM_SOPT7_ADC0ALTTRGEN_MASK  | // selects PDB not ALT trigger
                SIM_SOPT7_ADC0PRETRGSEL_MASK );
  SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);       // applies only in case of ALT trigger, in which case
  PDB0_SC =  PDB_SC_CONT_MASK       // Contintuous, rather than one-shot, mode
         | PDB_SC_PDBEN_MASK      // PDB enabled
//          | PDB_SC_PDBIE_MASK      // PDB Interrupt Enable
         | PDB_SC_PRESCALER(0x5)  // Slow down the period of the PDB for testing
         | PDB_SC_TRGSEL(0xf)     // Trigger source is Software Trigger to be invoked in this file
         | PDB_SC_MULT(2);        // Multiplication factor 20 for the prescale divider for the counter clock
                                  // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
  PDB0_IDLY = 0x0000;   // need to trigger interrupt every counter reset which happens when modulus reached
  PDB0_MOD = 0xffff;    // largest period possible with the slections above, so slow you can see each conversion.
// channel 0 pretrigger 0 and 1 enabled and delayed
  PDB0_CH0C1 = PDB_C1_EN(0x01)
           | PDB_C1_TOS(0x01)
           | PDB_C1_EN(0x02)
           | PDB_C1_TOS(0x02) ;
  PDB0_CH0DLY0 = 0x2000 ;
  PDB0_CH0DLY1 = 0x4000 ;
  PDB0_SC =  PDB_SC_CONT_MASK        // Contintuous, rather than one-shot, mode
         | PDB_SC_PDBEN_MASK       // PDB enabled
//          | PDB_SC_PDBIE_MASK       // PDB Interrupt Enable
         | PDB_SC_PRESCALER(0x5)   // Slow down the period of the PDB for testing
         | PDB_SC_TRGSEL(0xf)      // Trigger source is Software Trigger to be invoked in this file
         | PDB_SC_MULT(2)          // Multiplication factor 20 for the prescale divider for the counter clock
         | PDB_SC_LDOK_MASK;       // Need to ok the loading or it will not load certain regsiters!
                                   // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
 
  Master_Adc_Config.CONFIG1  = ADLPC_NORMAL
                            | ADC_CFG1_ADIV(ADIV_4)
                            | ADLSMP_LONG
                            | ADC_CFG1_MODE(MODE_16)
                            | ADC_CFG1_ADICLK(ADICLK_BUS);
  Master_Adc_Config.CONFIG2  = MUXSEL_ADCA
                            | ADACKEN_DISABLED
                            | ADHSC_HISPEED
                            | ADC_CFG2_ADLSTS(ADLSTS_20) ;
  Master_Adc_Config.STATUS2  = ADTRG_HW
                            | ACFE_DISABLED
                            | ACFGT_GREATER
                            | ACREN_ENABLED
                            | DMAEN_DISABLED
                            | ADC_SC2_REFSEL(REFSEL_EXT);
  Master_Adc_Config.STATUS3  = CAL_OFF
                            | ADCO_SINGLE
                            | AVGE_ENABLED
                            | ADC_SC3_AVGS(AVGS_32);
  Master_Adc_Config.PGA      = PGAEN_DISABLED
                            | PGACHP_NOCHOP
                            | PGALP_NORMAL
                            | ADC_PGA_PGAG(PGAG_64);
  Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
  Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
  ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config ADC
  ADC_Cal(ADC0_BASE_PTR);                    // do the calibration
  Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(26);
  Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(30);
  ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config ADC0
  enable_irq(ADC0_irq_no) ;  
  PDB0_SC |= PDB_SC_SWTRIG_MASK ;    // kick off the PDB  - just once

}

void adc0_isr(void){ if (( ADC0_SC1A & ADC_SC1_COCO_MASK ) == ADC_SC1_COCO_MASK) { 

  printf("ADC0A: %d\t",ADC0_RA);

 } else if (( ADC0_SC1B & ADC_SC1_COCO_MASK ) == ADC_SC1_COCO_MASK) {

  printf("ADC0B: %d\r",ADC0_RB);

 }}

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