SPI DMA issue for IXM6ULL

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SPI DMA issue for IXM6ULL

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liqi_wu
Contributor III

current I use IMX6ULL, I meat a SPI DMA issue.

I configated SPI as POL=0, PHA=1. When I use SPI polling to do data transfer, then it is OK.

But when I use SPI DMA to do data transfer,  then the SPI timing look like POL=0, PHA=0. 

what is wrong with it? is there something wrong configuration while in SPI DMA or in SPI DMA, IMX6ULL only support POL=0, PHA=0?

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liqi_wu
Contributor III

any update?

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igorpadykov
NXP Employee
NXP Employee

Hi liqi

what bsp used in the case, please try nxp official bsp from

source.codeaurora.org/external/imx/linux-imx  repository

linux-imx - i.MX Linux kernel 

Documentation

i.MX Software and Development Tools | NXP 

Best regards
igor
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liqi_wu
Contributor III

Hi igorpadykov,

No use bsp and no use linux. I just use the demo(sdma_b2b_transfer) in SDK_2.2_MCIM6ULL.

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igorpadykov
NXP Employee
NXP Employee

Hi liqi

please try to test on MX6ULL EVK board.


Best regards
igor

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liqi_wu
Contributor III

Hi igorpadykov,

 

any update for this case? or have you try it on IMX6ULL EVK board?

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liqi_wu
Contributor III

Hi <https://community.nxp.com/people/igorpadykov?et=watches.email.thread> igorpadykov,

Just as you said, I try it on the IMX6ULL EVK. But the result is same as I said in previously email. The timing is attached.

Have you also try it?

//SPI configuration: baudRate_Bps=20000000 burstLength = 32

static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config)

{

config->channelMode = kECSPI_Slave; /!< ECSPI peripheral operates in slave mode./

config->clockInactiveState = kECSPI_ClockInactiveStateLow; /*!< Clock line (SCLK) inactive state */

config->dataLineInactiveState = kECSPI_DataLineInactiveStateLow; /*!< Data line (MOSI&MISO) inactive state */

config->chipSlectActiveState = kECSPI_ChipSelectActiveStateLow; /*!< Chip select(SS) line active state */

config->waveForm = kECSPI_WaveFormSingle; /*!< ECSPI SS wave form */

config->polarity = kECSPI_PolarityActiveHigh; /*!< Clock polarity */

config->phase = kECSPI_ClockPhaseSecondEdge; /*!< clock phase */

}

Thanks!

wuliqi

发件人: bounces+210748-fda0-liqi_wu=163.com@jiveon.jivesoftware.com 代表 igorpadykov

发送时间: 2020年1月14日 14:39

收件人: liqi wu <liqi_wu@163.com>

主题: Re: - Re: SPI DMA issue for IXM6ULL

<https://community.freescale.com/resources/statics/1000/35400-NXP-Community-Email-banner-600x75.jpg> NXP Community

Re: SPI DMA issue for IXM6ULL

reply from igorpadykov <https://community.nxp.com/people/igorpadykov?et=watches.email.thread> in i.MX Processors - View the full discussion <https://community.nxp.com/message/1254956?commentID=1254956&et=watches.email.thread#comment-1254956>

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liqi_wu
Contributor III

Hi igorpadykov,

I will try it on IMX6ULL EVK board.

I hope you also can try it if possible.

发件人: bounces+210748-fda0-liqi_wu=163.com@jiveon.jivesoftware.com 代表 igorpadykov

发送时间: 2020年1月14日 14:39

收件人: liqi wu <liqi_wu@163.com>

主题: Re: - Re: SPI DMA issue for IXM6ULL

<https://community.freescale.com/resources/statics/1000/35400-NXP-Community-Email-banner-600x75.jpg> NXP Community

Re: SPI DMA issue for IXM6ULL

reply from igorpadykov <https://community.nxp.com/people/igorpadykov?et=watches.email.thread> in i.MX Processors - View the full discussion <https://community.nxp.com/message/1254956?commentID=1254956&et=watches.email.thread#comment-1254956>

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