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QN9020 : Internal flash write steps

Question asked by Tony Makkiel on Jan 9, 2020
Latest reply on Jan 21, 2020 by Mario Ignacio Castaneda Lopez


      I have some questions on the internal flash write am hoping someone could help with, please. 


1) On bootup, the power to the flash is enabled by default. But as soon as "plf_init" is called the power is disabled. So is it safe to assume QBlue stack, will enable the power to the flash whenever it needs to access the flash? 


2) Should the application enable the power to flash before it makes any NVDS api calls (nvds.h)? Or is it taken care of internally?


3) Section 5 of  UM10995, mentions using SRAM location (passed using plf_init) to read the flash location and then writing the data. Is the whole 4k byte read and written back with the updated data?


4) If it reads the 4k flash, how much time would be a typical write cycle take? I am thinking of how much time I need to set for the watchdog timer.


5) The document talks about using 4k area at the end of flash as backup information. When is this updated and read back?


6) Are the values on the NVDS updated immediately when a new value becomes available [ on the same handler/task ]? Or is it updated on the SRAM and updated later on a different handler?


7) According to, of  UM10995,  the SRAM location nvds_tmp_buf, can be NULL. How is the write operation handled in this case? Is this when it uses the 4k area at the end of flash?


Many Thanks,