DDR3 Config Setting in P1020RM

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DDR3 Config Setting in P1020RM

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alpesh_borad
Contributor I

Hello,

I am using P1020RM in my current design.

In design, there are Two DDR-3 memory connected with P1020RM.

In earlier design, it was working fine @200MHz clock frequency and below are the hardware setting for 200MHz clock,

  • Pin# AJ22, TSEC_1588_PULSE_OUT2 - kept Floating
  • Pin# AH21, TSEC_1588_PULSE_OUT1 - kept Floating
  • Pin# AG22, TSEC_1588_CLK_OUT - kept Floating

Now we want to increase the clock frequency to 333MHz and for that we made changes from code warrior QCVS for register setting and apply in our u-boot code but It's not working.

Below are the hardware setting for 333MHz clock,

  • Pin# AJ22, TSEC_1588_PULSE_OUT2 - kept Low
  • Pin# AH21, TSEC_1588_PULSE_OUT1 - kept Low
  • Pin# AG22, TSEC_1588_CLK_OUT - kept High

Observation:-

With some different register setting,

  • It shows error " D_INT time out. Memory may not work".

With some other different register setting,

  • It's not going further after DRAM INIT.

Can any one provide the correct register and hardware setting to work DDR-3 @333MHz clock frequency? 

DDR3 Part# AS4C512M8D3A-12BIN

Regards,

Alpesh.

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Bulat
NXP Employee
NXP Employee

It looks like you use 16-bit DDR3 bus width. Our developemnt boards have 32-bit memory bus, below is the memory dump of the DDR3 controller working at 333MHZ MCK frequency:

ffe02000: 0000003f 00000000 00000000 00000000
ffe02010: 00000000 00000000 00000000 00000000
ffe02080: 80014302 00000000 00000000 00000000
ffe02090: 00000000 00000000 00000000 00000000
ffe020a0: 00000000 00000000 00000000 00000000
ffe020b0: 00000000 00000000 00000000 00000000
ffe020c0: 00000000 00000000 00000000 00000000
ffe020d0: 00000000 00000000 00000000 00000000
ffe020e0: 00000000 00000000 00000000 00000000
ffe02020: 00000000 00000000 00000000 00000000
ffe02030: 00000000 00000000 00000000 00000000
ffe02040: 00000000 00000000 00000000 00000000
ffe02050: 00000000 00000000 00000000 00000000
ffe02060: 00000000 00000000 00000000 00000000
ffe02070: 00000000 00000000 00000000 00000000
ffe020f0: 00000000 00000000 00000000 00000000
ffe02100: 00020000 00110104 5d59e544 0fa888cd
ffe02110: c70c0008 24401000 00441210 00000000
ffe02120: 00000000 0a280100 deadbeef 00000000
ffe02130: 03000000 00000000 00000000 00000000
ffe02140: 00000000 00000000 00000000 00000000
ffe02150: 00000000 00000000 00000000 00000000
ffe02160: 00000001 01401400 00000000 00000000
ffe02170: 89080600 8675f608 00000000 00000000
ffe02180: 00000000 00000000 00000000 00000000
ffe02190: 00000000 00000000 00000000 00000000
ffe021a0: 00000000 00000000 00000000 00000000
ffe021b0: 00000000 00000000 00000000 00000000
ffe021c0: 00000000 00000000 00000000 00000000
ffe021d0: 00000000 00000000 00000000 00000000
ffe021e0: 00000000 00000000 00000000 00000000
ffe021f0: 00000000 00000000 00000000 00000000

Regards,

Bulat

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alpesh_borad
Contributor I

Hello Bulat,

Thank you very much for your response.

We used your value but unfortunately that did not work for me.

We have modified some registers' value from your value which work for me.

Below is the table showing all registers' value which we used for 333MHz clock frequency.

Offset address (hex)Register nameValue for 333MHz
2000DDR_CS0_BNDS0x0000003F
2008DDR_CS1_BNDS0x00000000
2080DDR_CS0_CONFIG0x80014402
2084DDR_CS1_CONFIG0x00000000
20C0DDR_CS0_CONFIG_20x00000000
20C4DDR_CS1_CONFIG_20x00000000
2100DDR_TIMING_CFG_30x00050000
2104DDR_TIMING_CFG_00x00110104
2108DDR_TIMING_CFG_10x5D592544
210CDDR_TIMING_CFG_20x0FA890CD
2110DDR_DDR_SDRAM_CFG0xC7140008
2114DDR_DDR_SDRAM_CFG_20x24401010
2118DDR_DDR_SDRAM_MODE0x00441210
211CDDR_DDR_SDRAM_MODE_20x00000000
2120DDR_DDR_SDRAM_MD_CNTL0x00000000
2124DDR_DDR_SDRAM_INTERVAL0x0A280100
2128DDR_DDR_DATA_INIT0xDEADBEEF
2130DDR_DDR_SDRAM_CLK_CNTL0x03000000
2148DDR_DDR_INIT_ADDR0x00000000
214CDDR_DDR_INIT_EXT_ADDR0x00000000
2160DDR_TIMING_CFG_40x00000001
2164DDR_TIMING_CFG_50x01401400
2170DDR_DDR_ZQ_CNTL0x89080600
2174DDR_DDR_WRLVL_CNTL0x8675F608
217CDDR_DDR_SR_CNTR0x00000000
2180DDR_DDR_SDRAM_RCW_10x00000000
2184DDR_DDR_SDRAM_RCW_20x00000000

Thanks again.

Regards,

Alpesh.

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Bulat
NXP Employee
NXP Employee

Of course values needed to be modified in accordance with your bus width and specific DDR3 device parameters. Am I correct that DDR3 memory is now working?

Regards,

Bulat

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alpesh_borad
Contributor I

Hello Bulat,

Yes, You're right.

The DDR-3 memory is now working with this new settings.

Thanks again.

Regards,

Alpesh.

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