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Need processor timings for DDR3 simulation in Hyperlynx

Question asked by Faiz Majeed on Dec 18, 2019
Latest reply on Dec 18, 2019 by Bulat Karymov

HI!

I am designing a custom board using T1042 processor. During the PCB designing of DDR3, i have to run some simulations on hyperlynx software using DDR batch simulation. i get all the results pass at 400 clock frequency (800MT/S). for other frequencies i got setup time voilation. i think there is some problem in the timing model file loaded for controller into the software. 

Here is the data in that text file that contain timing models. can you provide me exact values that T1042 has so that i should be able to simulate it on 1600MT/s. for now i think this model support only simulations at 800MT/s.

mainly i need setup time, hold time, and 3 other parameters that i have highlighted below.

Thanks

DDR3: AS4C512M16D3L-12BIN

 

/****************************************************************************************
* HyperLynx DDR Controller Timing Model
****************************************************************************************/

`timescale 1ps / 1ps // do not change

 

// top-level module definition and interface ports
// ...the port names are HyperLynx standard names...do not change
module ddr3_ctl (
output ck,
output addr_cmd,
output ctl,
output dm,
inout dq,
inout dqs
);

/****************************************************************************************
* HyperLynx DDR Controller Timing Model Parameters
*
* A controller timing model should define the following parameters:
*
* All cycles:
* tACCSkew Output delay skew from CK falling to Addr/Cmd/Ctl (+/-)
*
* Write cycles:
* tCKDQS Output delay skew from CK rising to DQS rising (+/-)
* tDQSDQQ Output delay skew from DQS to DQ (+/-)
*
* Read cycles
* tDS Minimum DQ to DQS setup time, with 1/4 cycle DQS shift
* tDH Minimum DQS to DQ hold time, with 1/4 cycle DQS shift
*
****************************************************************************************/


// Timing parameters by speed grade
`ifdef DDR_266
parameter tACCSkew = 1000;
parameter tCKDQS = 1000;
parameter tDQSDQQ = 500;
parameter tDS = 500;
parameter tDH = 500;
`elsif DDR_333
parameter tACCSkew = 800;
parameter tCKDQS = 800;
parameter tDQSDQQ = 400;
parameter tDS = 400;
parameter tDH = 400;
`else `define DDR_400
parameter tACCSkew = 600;
parameter tCKDQS = 600;
parameter tDQSDQQ = 300;
parameter tDS = 300;
parameter tDH = 300;
`endif


/****************************************************************************************
* Default values, in case something slips through undefined...
****************************************************************************************/
`ifndef tCK
`define tCK 2500
`endif

 

/****************************************************************************************
* Derived timing parameters
****************************************************************************************/
parameter tACDlyMin = `tCK/2 - tACCSkew; // Delay from CK rising out to Addr/Cmd/Ctl invalid (min)
parameter tACDlyMax = `tCK/2 + tACCSkew; // Delay from CK rising out to Addr/Cmd/Ctl invalid (max)

parameter tCKCTLMin = -`tCK + tACDlyMin; // CK rising out to earliest valid CTL (CK-1)
parameter tCKCTLMax = -`tCK + tACDlyMax; // CK rising out to latest valid CTL (CK-1)

`ifdef ADDRCMD2T
parameter tCKACmin = -(2*`tCK) + tACDlyMin; // CK rising out to earliest valid ADDR/CMD (CK-2)
parameter tCKACmax = -(2*`tCK) + tACDlyMax; // CK rising out to latest valid ADDR/CMD (CK-2)
`else `define ADDRCMD1T
parameter tCKACmin = -`tCK + tACDlyMin; // CK rising out to earliest valid ADDR/CMD (CK-1)
parameter tCKACmax = -`tCK + tACDlyMax; // CK rising out to latest valid ADDR/CMD (CK-1)
`endif

parameter tDQBit = `tCK / 2; // Data bit time
parameter tDQPrelaunch = -tDQBit/2; // Data bit pre-launch shift (Write to DRAM)
parameter tDQSDQmin = tDQPrelaunch-tDQSDQQ; // DQS out to earliest valid DQ/DM (write to DRAM)
parameter tDQSDQmax = tDQPrelaunch+tDQSDQQ; // DQS out to latest valid DQ/DM (write to DRAM)


/****************************************************************************************
* Timing relationships
****************************************************************************************/
specify

// ADDR/CMD prelaunch window from next CK (1T or 2T)
$delay(posedge ck, addr_cmd, tCKACmin, tCKACmax);
// CTL prelaunch window from next CK (1T always)
$delay(posedge ck, ctl, tCKCTLmin, tCKCTLmax);

// DRAM Write cycles
$delay(ck, dqs, -tCKDQS, tCKDQS);
$delay(dqs, dq, tDQSDQmin, tDQSDQmax);
$delay(dqs, dm, tDQSDQmin, tDQSDQmax);

// DRAM Read cycles
$setuphold(dqs, dq, tDS, tDH);

endspecify

endmodule

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