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Errors using OpenSDA running lpc4322_mimxrt1010_evk_qspi_if_crc on MIMXRT1010-EVK

Question asked by Kevin Chevens on Dec 11, 2019
Latest reply on Dec 13, 2019 by jeremyzhou

Hi

I trying to get to a position where I can debug an MIMXRT1010-EVK via the OpenSDA. I can debug via an external J-Link probe fine. However the there is something I'm doing wrong with OpenSDA.

 

From cmd window 1:

C:\Users\kevin\AppData\Roaming\xPacks\OpenOCD\0.10.0-13\bin>openocd -f interface
/cmsis-dap.cfg -f board/nxp_mimxrt1010_2.cfg -d -l test.txt
xPack OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev (2019-07-17-11:28)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 13 3 options.c:60 configuration_output_handler(): debug_level: 3
User : 14 8 options.c:60 configuration_output_handler():
Debug: 15 12 command.c:143 script_debug(): command - log_output log_output test.
txt

 

From cmd window 2:

C:\Tools\GNU\ARM\7-2017q4\bin>arm-none-eabi-gdb.exe
GNU gdb (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 8.0.50.20171128-
git
Copyright (C) 2017 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-w64-mingw32 --target=arm-none-eabi".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
(gdb) target remote localhost:3333
Remote debugging using localhost:3333
warning: No executable has been specified and target does not support
determining executable automatically. Try using the "file" command.
0x60002d20 in ?? ()
(gdb) disconnect
Ending remote debugging.

 

The resulting log file:

Debug: 17 18 options.c:184 add_default_dirs(): bindir=bin
Debug: 18 18 options.c:185 add_default_dirs(): pkgdatadir=
Debug: 19 18 options.c:186 add_default_dirs(): exepath=C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin
Debug: 20 18 options.c:187 add_default_dirs(): bin2data=../
Debug: 21 18 configuration.c:42 add_script_search_dir(): adding C:\Users\kevin\AppData\Roaming/OpenOCD
Debug: 22 19 configuration.c:42 add_script_search_dir(): adding C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin/..//site
Debug: 23 19 configuration.c:42 add_script_search_dir(): adding C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin/..//scripts
Debug: 24 20 configuration.c:97 find_file(): found C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin/..//scripts/interface/cmsis-dap.cfg
Debug: 25 21 command.c:143 script_debug(): command - interface interface cmsis-dap
Debug: 27 21 command.c:355 register_command_handler(): registering 'cmsis-dap'...
Debug: 28 21 command.c:355 register_command_handler(): registering 'cmsis-dap'...
Debug: 29 21 command.c:355 register_command_handler(): registering 'cmsis_dap_vid_pid'...
Debug: 30 21 command.c:355 register_command_handler(): registering 'cmsis_dap_serial'...
Debug: 31 21 configuration.c:97 find_file(): found C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin/..//scripts/board/nxp_mimxrt1010_2.cfg
Debug: 32 22 configuration.c:97 find_file(): found C:/Users/kevin/AppData/Roaming/xPacks/OpenOCD/0.10.0-13/bin/..//scripts/target/swj-dp.tcl
Debug: 33 22 command.c:143 script_debug(): command - transport transport select
Info : 34 22 transport.c:286 jim_transport_select(): auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
Debug: 35 22 command.c:355 register_command_handler(): registering 'swd'...
Debug: 36 22 command.c:143 script_debug(): command - transport transport select swd
Warn : 37 22 transport.c:297 jim_transport_select(): Transport "swd" was already selected
Debug: 38 22 command.c:143 script_debug(): command - transport transport select
Debug: 39 22 command.c:143 script_debug(): command - transport transport select
Debug: 40 22 command.c:143 script_debug(): command - transport transport select
Debug: 41 22 command.c:143 script_debug(): command - transport transport select
Debug: 42 22 command.c:143 script_debug(): command - swd swd newdap mimxrt1011 cpu -irlen 4 -expected-id 0x0bd11477
Debug: 43 22 tcl.c:567 jim_newtap_cmd(): Creating New Tap, Chip: mimxrt1011, Tap: cpu, Dotted: mimxrt1011.cpu, 4 params
Debug: 44 22 core.c:1304 jtag_tap_init(): Created Tap: mimxrt1011.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0
Debug: 45 22 command.c:143 script_debug(): command - dap dap create mimxrt1011.dap -chain-position mimxrt1011.cpu
Debug: 46 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 47 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 48 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 49 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 50 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 51 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 52 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 53 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 54 22 command.c:355 register_command_handler(): registering 'mimxrt1011.dap'...
Debug: 55 22 command.c:143 script_debug(): command - target target create mimxrt1011.cpu cortex_m -dap mimxrt1011.dap
Debug: 56 22 command.c:355 register_command_handler(): registering 'arm'...
Debug: 57 22 command.c:355 register_command_handler(): registering 'arm'...
Debug: 58 22 command.c:355 register_command_handler(): registering 'arm'...
Debug: 59 22 command.c:355 register_command_handler(): registering 'arm'...
Debug: 60 22 command.c:355 register_command_handler(): registering 'arm'...
Debug: 61 23 command.c:355 register_command_handler(): registering 'arm'...
Debug: 62 23 command.c:355 register_command_handler(): registering 'arm'...
Debug: 63 23 command.c:355 register_command_handler(): registering 'arm'...
Debug: 64 23 command.c:355 register_command_handler(): registering 'arm'...
Debug: 65 23 command.c:355 register_command_handler(): registering 'tpiu'...
Debug: 66 23 command.c:355 register_command_handler(): registering 'itm'...
Debug: 67 23 command.c:355 register_command_handler(): registering 'itm'...
Debug: 68 23 command.c:355 register_command_handler(): registering 'cortex_m'...
Debug: 69 23 command.c:355 register_command_handler(): registering 'cortex_m'...
Debug: 70 23 command.c:355 register_command_handler(): registering 'cortex_m'...
Debug: 71 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 72 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 73 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 74 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 75 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 76 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 77 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 78 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 79 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 80 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 81 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 82 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 83 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 84 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 85 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 86 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 87 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 88 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 89 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 90 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 91 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 92 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 93 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 94 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 95 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 96 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 97 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 98 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 99 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 100 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 101 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 102 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 103 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 104 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 105 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 106 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 107 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 108 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 109 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 110 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 111 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 112 23 command.c:355 register_command_handler(): registering 'mimxrt1011.cpu'...
Debug: 113 23 command.c:143 script_debug(): command - transport transport select
Debug: 114 23 command.c:143 script_debug(): command - cortex_m cortex_m reset_config sysresetreq
Debug: 116 23 command.c:143 script_debug(): command - adapter_khz adapter_khz 1000
Debug: 118 23 core.c:1636 jtag_config_khz(): handle jtag khz
Debug: 119 23 core.c:1599 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 120 23 core.c:1599 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 121 23 options.c:60 configuration_output_handler(): adapter speed: 1000 kHz
User : 122 23 options.c:60 configuration_output_handler():
Info : 123 24 server.c:311 add_service(): Listening on port 6666 for tcl connections
Info : 124 24 server.c:311 add_service(): Listening on port 4444 for telnet connections
Debug: 125 24 command.c:143 script_debug(): command - init init
Debug: 127 24 command.c:143 script_debug(): command - target target init
Debug: 129 24 command.c:143 script_debug(): command - target target names
Debug: 130 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu cget -event gdb-flash-erase-start
Debug: 131 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu configure -event gdb-flash-erase-start reset init
Debug: 132 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu cget -event gdb-flash-write-end
Debug: 133 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu configure -event gdb-flash-write-end reset halt
Debug: 134 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu cget -event gdb-attach
Debug: 135 24 command.c:143 script_debug(): command - mimxrt1011.cpu mimxrt1011.cpu configure -event gdb-attach halt
Debug: 136 24 target.c:1404 handle_target_init_command(): Initializing targets...
Debug: 137 24 semihosting_common.c:97 semihosting_common_init():
Debug: 138 25 command.c:355 register_command_handler(): registering 'target_request'...
Debug: 139 25 command.c:355 register_command_handler(): registering 'trace'...
Debug: 140 25 command.c:355 register_command_handler(): registering 'trace'...
Debug: 141 25 command.c:355 register_command_handler(): registering 'fast_load_image'...
Debug: 142 25 command.c:355 register_command_handler(): registering 'fast_load'...
Debug: 143 25 command.c:355 register_command_handler(): registering 'profile'...
Debug: 144 25 command.c:355 register_command_handler(): registering 'virt2phys'...
Debug: 145 25 command.c:355 register_command_handler(): registering 'reg'...
Debug: 146 25 command.c:355 register_command_handler(): registering 'poll'...
Debug: 147 25 command.c:355 register_command_handler(): registering 'wait_halt'...
Debug: 148 25 command.c:355 register_command_handler(): registering 'halt'...
Debug: 149 25 command.c:355 register_command_handler(): registering 'resume'...
Debug: 150 25 command.c:355 register_command_handler(): registering 'reset'...
Debug: 151 25 command.c:355 register_command_handler(): registering 'soft_reset_halt'...
Debug: 152 25 command.c:355 register_command_handler(): registering 'step'...
Debug: 153 25 command.c:355 register_command_handler(): registering 'mdd'...
Debug: 154 25 command.c:355 register_command_handler(): registering 'mdw'...
Debug: 155 25 command.c:355 register_command_handler(): registering 'mdh'...
Debug: 156 25 command.c:355 register_command_handler(): registering 'mdb'...
Debug: 157 25 command.c:355 register_command_handler(): registering 'mwd'...
Debug: 158 25 command.c:355 register_command_handler(): registering 'mww'...
Debug: 159 25 command.c:355 register_command_handler(): registering 'mwh'...
Debug: 160 25 command.c:355 register_command_handler(): registering 'mwb'...
Debug: 161 25 command.c:355 register_command_handler(): registering 'bp'...
Debug: 162 25 command.c:355 register_command_handler(): registering 'rbp'...
Debug: 163 25 command.c:355 register_command_handler(): registering 'wp'...
Debug: 164 25 command.c:355 register_command_handler(): registering 'rwp'...
Debug: 165 25 command.c:355 register_command_handler(): registering 'load_image'...
Debug: 166 25 command.c:355 register_command_handler(): registering 'dump_image'...
Debug: 167 25 command.c:355 register_command_handler(): registering 'verify_image_checksum'...
Debug: 168 25 command.c:355 register_command_handler(): registering 'verify_image'...
Debug: 169 25 command.c:355 register_command_handler(): registering 'test_image'...
Debug: 170 25 command.c:355 register_command_handler(): registering 'reset_nag'...
Debug: 171 25 command.c:355 register_command_handler(): registering 'ps'...
Debug: 172 25 command.c:355 register_command_handler(): registering 'test_mem_access'...
Debug: 173 35 cmsis_dap_usb.c:251 cmsis_dap_usb_open(): Cannot read product string of device 0x413c:0xabce
Info : 174 41 cmsis_dap_usb.c:874 cmsis_dap_get_caps_info(): CMSIS-DAP: SWD Supported
Info : 175 43 cmsis_dap_usb.c:854 cmsis_dap_get_version_info(): CMSIS-DAP: FW Version = 1.10
Info : 176 47 cmsis_dap_usb.c:967 cmsis_dap_swd_open(): CMSIS-DAP: Interface Initialised (SWD)
Debug: 177 48 cmsis_dap_usb.c:1039 cmsis_dap_init(): CMSIS-DAP: Packet Size = 64
Debug: 178 51 cmsis_dap_usb.c:1052 cmsis_dap_init(): CMSIS-DAP: Packet Count = 1
Debug: 179 51 cmsis_dap_usb.c:1055 cmsis_dap_init(): Allocating FIFO for 1 pending HID requests
Info : 180 53 cmsis_dap_usb.c:895 cmsis_dap_get_status(): SWCLK/TCK = 0 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : 181 63 cmsis_dap_usb.c:1108 cmsis_dap_init(): CMSIS-DAP: Interface ready
Debug: 182 63 core.c:1599 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 183 63 core.c:1603 adapter_khz_to_speed(): have interface set up
Debug: 184 65 core.c:1599 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 185 65 core.c:1603 adapter_khz_to_speed(): have interface set up
Info : 186 65 core.c:1381 adapter_init(): clock speed 1000 kHz
Debug: 187 65 openocd.c:158 handle_init_command(): Debug Adapter init complete
Debug: 188 65 command.c:143 script_debug(): command - transport transport init
Debug: 190 65 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 191 65 command.c:143 script_debug(): command - dap dap init
Debug: 193 65 arm_dap.c:105 dap_init_all(): Initializing all DAPs ...
Debug: 194 69 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Info : 195 75 adi_v5_swd.c:136 swd_connect(): SWD DPIDR 0x0bd11477
Debug: 196 75 arm_adi_v5.c:653 dap_dp_init(): mimxrt1011.dap
Debug: 197 77 arm_adi_v5.c:698 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 198 77 arm_adi_v5.h:467 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 199 79 arm_adi_v5.c:706 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 200 79 arm_adi_v5.h:467 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 201 81 cmsis_dap_usb.c:678 cmsis_dap_swd_write_from_queue(): refusing to enable sticky overrun detection
Debug: 202 83 openocd.c:175 handle_init_command(): Examining targets...
Debug: 203 83 target.c:1591 target_call_event_callbacks(): target event 17 (examine-start)
Debug: 204 85 arm_adi_v5.c:922 dap_find_ap(): Found AHB3-AP at AP index: 0 (IDR=0x04770041)
Debug: 205 86 arm_adi_v5.c:777 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 206 87 arm_adi_v5.c:788 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 207 89 target.c:2357 target_read_u32(): address: 0xe000ed00, value: 0x411fc272
Debug: 208 89 cortex_m.c:2167 cortex_m_examine(): Cortex-M7 r1p2 processor detected
Debug: 209 89 cortex_m.c:2178 cortex_m_examine(): cpuid: 0x411fc272
Debug: 210 91 target.c:2357 target_read_u32(): address: 0xe000ef40, value: 0x10110021
Debug: 211 93 target.c:2357 target_read_u32(): address: 0xe000ef44, value: 0x11000011
Debug: 212 93 cortex_m.c:2198 cortex_m_examine(): Cortex-M7 floating point feature FPv5_SP found
Debug: 213 93 target.c:2445 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 214 97 target.c:2357 target_read_u32(): address: 0xe0002000, value: 0x10000080
Debug: 215 97 target.c:2445 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 216 99 target.c:2445 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 217 101 target.c:2445 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 218 103 target.c:2445 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 219 105 target.c:2445 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 220 107 target.c:2445 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 221 109 target.c:2445 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 222 111 target.c:2445 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 223 113 cortex_m.c:2270 cortex_m_examine(): FPB fpcr 0x10000080, numcode 8, numlit 0
Debug: 224 115 target.c:2357 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 225 115 cortex_m.c:2004 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000
Debug: 226 117 target.c:2357 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
Debug: 227 117 cortex_m.c:2011 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
Debug: 228 117 target.c:2445 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 229 119 target.c:2445 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 230 121 target.c:2445 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 231 123 target.c:2445 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 232 125 cortex_m.c:2060 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 233 125 cortex_m.c:2280 cortex_m_examine(): mimxrt1011.cpu: hardware has 8 breakpoints, 4 watchpoints
Debug: 234 125 target.c:1591 target_call_event_callbacks(): target event 18 (examine-end)
Debug: 235 125 command.c:143 script_debug(): command - flash flash init
Info : 236 127 cortex_m.c:595 cortex_m_poll(): mimxrt1011.cpu: external reset detected
Debug: 238 127 tcl.c:1222 handle_flash_init_command(): Initializing flash devices...
Debug: 239 127 command.c:143 script_debug(): command - mflash mflash init
Debug: 240 129 cortex_m.c:605 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x10000
Debug: 241 131 cortex_m.c:300 cortex_m_endreset_event(): DCB_DEMCR = 0x01000000
Debug: 242 135 target.c:2445 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 243 139 target.c:2357 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 244 139 target.c:2445 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 245 141 target.c:2445 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 246 143 target.c:2445 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 247 145 target.c:2445 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 248 147 target.c:2445 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 249 149 target.c:2445 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 250 151 target.c:2445 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 251 153 target.c:2445 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 252 155 target.c:2445 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 253 157 target.c:2445 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 254 159 target.c:2445 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 255 161 target.c:2445 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 256 163 target.c:2445 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 257 165 target.c:2445 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 258 167 target.c:2445 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 259 169 target.c:2445 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 260 171 target.c:2445 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 261 173 target.c:2445 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 262 175 target.c:2445 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 263 177 target.c:2445 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 265 181 mflash.c:1378 handle_mflash_init_command(): Initializing mflash devices...
Debug: 266 181 command.c:143 script_debug(): command - nand nand init
Debug: 268 183 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 269 183 command.c:143 script_debug(): command - pld pld init
Debug: 271 185 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Debug: 272 186 gdb_server.c:3386 gdb_target_start(): starting gdb server for mimxrt1011.cpu on 3333
Info : 273 186 server.c:311 add_service(): Listening on port 3333 for gdb connections
Info : 274 47715 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 275 47716 breakpoints.c:356 breakpoint_clear_target_internal(): Delete all breakpoints for target: mimxrt1011.cpu
Debug: 276 47716 breakpoints.c:496 watchpoint_clear_target(): Delete all watchpoints for target: mimxrt1011.cpu
Debug: 277 47720 target.c:1591 target_call_event_callbacks(): target event 19 (gdb-attach)
Debug: 278 47720 target.c:4539 target_handle_event(): target(0): mimxrt1011.cpu (cortex_m) event: 19 (gdb-attach) action: halt
Debug: 279 47720 command.c:143 script_debug(): command - halt halt
Debug: 281 47723 target.c:3028 handle_halt_command(): -
Debug: 282 47723 cortex_m.c:670 cortex_m_halt(): target->state: running
Debug: 283 47727 cortex_m.c:482 cortex_m_debug_entry():
Debug: 284 47733 cortex_m.c:234 cortex_m_clear_halt(): NVIC_DFSR 0x1
Debug: 285 47737 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 0 value 0x61803001
Debug: 286 47739 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 1 value 0x0
Debug: 287 47741 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 2 value 0x17
Debug: 288 47743 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 3 value 0xfffffffc
Debug: 289 47745 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 4 value 0x400fc000
Debug: 290 47747 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 5 value 0x0
Debug: 291 47749 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 6 value 0x1e511bda
Debug: 292 47751 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 7 value 0x0
Debug: 293 47753 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 8 value 0x2001e0
Debug: 294 47755 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 9 value 0x0
Debug: 295 47757 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 10 value 0x1fff8000
Debug: 296 47759 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 11 value 0x0
Debug: 297 47761 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 12 value 0x0
Debug: 298 47763 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 13 value 0x20007fe8
Debug: 299 47765 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 14 value 0x60002d1f
Debug: 300 47767 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 15 value 0x60002d20
Debug: 301 47769 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 16 value 0x61000000
Debug: 302 47771 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 17 value 0x20007fe8
Debug: 303 47773 cortex_m.c:1611 cortex_m_load_core_reg_u32(): load from core reg 18 value 0x20008000
Debug: 304 47775 cortex_m.c:1665 cortex_m_load_core_reg_u32(): load from special reg 19 value 0x0
Debug: 305 47777 cortex_m.c:1665 cortex_m_load_core_reg_u32(): load from special reg 20 value 0x0
Debug: 306 47779 cortex_m.c:1665 cortex_m_load_core_reg_u32(): load from special reg 21 value 0x0
Debug: 307 47781 cortex_m.c:1665 cortex_m_load_core_reg_u32(): load from special reg 22 value 0x0
Debug: 308 47781 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000040
Debug: 309 47785 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 310 47785 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S0 value 0x0
Debug: 311 47785 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000041
Debug: 312 47789 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 313 47789 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S1 value 0x0
Debug: 314 47789 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000042
Debug: 315 47793 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 316 47793 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S2 value 0x0
Debug: 317 47793 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000043
Debug: 318 47797 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 319 47797 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S3 value 0x0
Debug: 320 47797 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000044
Debug: 321 47801 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 322 47801 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S4 value 0x0
Debug: 323 47801 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000045
Debug: 324 47805 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 325 47805 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S5 value 0x0
Debug: 326 47805 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000046
Debug: 327 47809 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 328 47809 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S6 value 0x0
Debug: 329 47809 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000047
Debug: 330 47813 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 331 47813 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S7 value 0x0
Debug: 332 47813 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000048
Debug: 333 47817 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 334 47817 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S8 value 0x0
Debug: 335 47817 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000049
Debug: 336 47821 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 337 47821 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S9 value 0x0
Debug: 338 47821 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004a
Debug: 339 47825 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 340 47825 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S10 value 0x0
Debug: 341 47825 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004b
Debug: 342 47829 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 343 47829 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S11 value 0x0
Debug: 344 47829 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004c
Debug: 345 47832 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 346 47833 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S12 value 0x0
Debug: 347 47833 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004d
Debug: 348 47836 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 349 47837 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S13 value 0x0
Debug: 350 47837 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004e
Debug: 351 47840 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 352 47841 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S14 value 0x0
Debug: 353 47841 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000004f
Debug: 354 47844 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0xffffffff
Debug: 355 47845 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S15 value 0xffffffff
Debug: 356 47845 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000050
Debug: 357 47848 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 358 47849 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S16 value 0x0
Debug: 359 47849 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000051
Debug: 360 47852 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 361 47853 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S17 value 0x0
Debug: 362 47853 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000052
Debug: 363 47857 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 364 47857 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S18 value 0x0
Debug: 365 47857 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000053
Debug: 366 47861 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 367 47861 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S19 value 0x0
Debug: 368 47861 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000054
Debug: 369 47865 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 370 47865 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S20 value 0x0
Debug: 371 47865 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000055
Debug: 372 47869 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 373 47869 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S21 value 0x0
Debug: 374 47869 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000056
Debug: 375 47873 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 376 47873 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S22 value 0x0
Debug: 377 47873 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000057
Debug: 378 47877 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 379 47877 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S23 value 0x0
Debug: 380 47877 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000058
Debug: 381 47881 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 382 47881 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S24 value 0x0
Debug: 383 47881 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000059
Debug: 384 47885 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 385 47885 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S25 value 0x0
Debug: 386 47885 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005a
Debug: 387 47889 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 388 47889 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S26 value 0x0
Debug: 389 47889 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005b
Debug: 390 47893 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 391 47893 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S27 value 0x0
Debug: 392 47893 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005c
Debug: 393 47897 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 394 47897 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S28 value 0x0
Debug: 395 47897 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005d
Debug: 396 47901 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 397 47901 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S29 value 0x0
Debug: 398 47901 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005e
Debug: 399 47905 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 400 47905 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S30 value 0x0
Debug: 401 47905 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x0000005f
Debug: 402 47909 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0xffffffff
Debug: 403 47909 cortex_m.c:1634 cortex_m_load_core_reg_u32(): load from FPU reg S31 value 0xffffffff
Debug: 404 47909 target.c:2445 target_write_u32(): address: 0xe000edf4, value: 0x00000021
Debug: 405 47913 target.c:2357 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 406 47913 cortex_m.c:1622 cortex_m_load_core_reg_u32(): load from FPSCR value 0x0
Debug: 407 47913 cortex_m.c:546 cortex_m_debug_entry(): entered debug state in core mode: Thread at PC 0x60002d20, target->state: halted
Debug: 408 47913 target.c:1591 target_call_event_callbacks(): target event 0 (gdb-halt)
Debug: 409 47913 target.c:1591 target_call_event_callbacks(): target event 1 (halted)
User : 410 47913 armv7m.c:581 armv7m_arch_state(): target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x60002d20 msp: 0x20007fe8
Debug: 411 47913 gdb_server.c:1010 gdb_new_connection(): New GDB Connection: 1, Target mimxrt1011.cpu, state: halted
Debug: 412 47913 gdb_server.c:3153 gdb_input_inner(): received packet: 'qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+'
Debug: 413 47916 gdb_server.c:3153 gdb_input_inner(): received packet: 'vMustReplyEmpty'
Debug: 414 47917 gdb_server.c:3153 gdb_input_inner(): received packet: 'QStartNoAckMode'
Debug: 415 47917 gdb_server.c:641 gdb_get_packet_inner(): Received first acknowledgment after entering noack mode. Ignoring it.
Debug: 416 47918 gdb_server.c:3153 gdb_input_inner(): received packet: 'Hg0'
Debug: 417 47918 gdb_server.c:3153 gdb_input_inner(): received packet: 'qXfer:features:read:target.xml:0,fff'
Debug: 418 47922 gdb_server.c:3153 gdb_input_inner(): received packet: 'qTStatus'
Debug: 419 47923 gdb_server.c:3153 gdb_input_inner(): received packet: '?'
Debug: 420 47923 gdb_server.c:3153 gdb_input_inner(): received packet: 'qXfer:threads:read::0,fff'
Debug: 421 47924 gdb_server.c:3153 gdb_input_inner(): received packet: 'Hc-1'
Debug: 422 47924 gdb_server.c:3153 gdb_input_inner(): received packet: 'qC'
Debug: 423 47925 gdb_server.c:3153 gdb_input_inner(): received packet: 'qAttached'
Debug: 424 47953 gdb_server.c:3153 gdb_input_inner(): received packet: 'g'
Debug: 425 47954 gdb_server.c:3153 gdb_input_inner(): received packet: 'qXfer:threads:read::0,fff'
Debug: 426 47955 gdb_server.c:3153 gdb_input_inner(): received packet: 'm60002d20,4'
Debug: 427 47955 gdb_server.c:1438 gdb_read_memory_packet(): addr: 0x0000000060002d20, len: 0x00000004
Debug: 428 47955 target.c:2210 target_read_buffer(): reading buffer of 4 byte at 0x60002d20
Debug: 429 47958 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 3 WAIT
Debug: 430 47962 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 431 47969 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Error: 432 47969 arm_adi_v5.c:548 mem_ap_read(): Failed to read memory and, additionally, failed to find out where
Debug: 433 47969 gdb_server.c:3153 gdb_input_inner(): received packet: 'm60002d20,2'
Debug: 434 47969 gdb_server.c:1438 gdb_read_memory_packet(): addr: 0x0000000060002d20, len: 0x00000002
Debug: 435 47969 target.c:2210 target_read_buffer(): reading buffer of 2 byte at 0x60002d20
Debug: 436 47974 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 437 47981 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Debug: 438 47985 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 439 47992 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Error: 440 47992 arm_adi_v5.c:548 mem_ap_read(): Failed to read memory and, additionally, failed to find out where
Debug: 441 48096 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 442 48103 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Debug: 443 48103 target.c:1591 target_call_event_callbacks(): target event 0 (gdb-halt)
User : 444 48103 target.c:2794 handle_target(): Polling target mimxrt1011.cpu failed, trying to reexamine
Debug: 445 48103 target.c:1591 target_call_event_callbacks(): target event 17 (examine-start)
Debug: 446 48107 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 447 48114 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Debug: 448 48117 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 449 48125 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Error: 450 48125 cortex_m.c:2126 cortex_m_examine(): Could not find MEM-AP to control the core
User : 451 48125 target.c:2802 handle_target(): Examination failed, GDB will be halted. Polling again in 100ms
Debug: 452 48330 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 453 48337 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Debug: 454 48337 target.c:1591 target_call_event_callbacks(): target event 0 (gdb-halt)
User : 455 48337 target.c:2794 handle_target(): Polling target mimxrt1011.cpu failed, trying to reexamine
Debug: 456 48337 target.c:1591 target_call_event_callbacks(): target event 17 (examine-start)
Debug: 457 48341 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 458 48348 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Debug: 459 48352 cmsis_dap_usb.c:929 cmsis_dap_swd_switch_seq(): JTAG-to-SWD
Debug: 460 48359 cmsis_dap_usb.c:733 cmsis_dap_swd_read_process(): SWD ack not OK @ 2 WAIT
Error: 461 48359 cortex_m.c:2126 cortex_m_examine(): Could not find MEM-AP to control the core
User : 462 48359 target.c:2802 handle_target(): Examination failed, GDB will be halted. Polling again in 300ms

 

the board cfg file is my attempt at what is required (so is probably wrong):

#
# NXP i.MX RT1011 family (Arm Cortex-M7 @ 600 MHz)
#

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME mimxrt1011
}

source [find target/swj-dp.tcl]

# use on-board SWD header
transport select swd

if { [info exists CPU_SWD_TAPID] } {
set _CPU_SWD_TAPID $CPU_SWD_TAPID
} else {
set _CPU_SWD_TAPID 0x0bd11477
}

if { [using_jtag] } {
set _CPU_TAPID 0
} else {
set _CPU_TAPID $_CPU_SWD_TAPID
}

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID

set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap


if { ![using_hla] } {
cortex_m reset_config sysresetreq
}

adapter_khz 1000

 

Hoping that someone has seen these errors before or can give some insight. Apologies for the lengthy post

 

Thanks in advance.

Outcomes