hi,
I am using mpc8358e power processor. I am going to use ddr sdram memory where i struck at configuring cpo , caslat and write_delay timings config.
*operating freq: 133Mhz
*memory: CL=3
can anyone tell me how to calculate cpo , write delay and caslat timings ??
thank you.
regards,
venkat.
Method of CPO calculation can be found in the AN2583 app note.
WR_DATA_DELAY should be set to the same time as CLK_ADJUST, typically 1/2 clock cycle.
CASLAT should be set to 3 clock cycles in your case, i.e. CASLAT=4b0101.
Below are the setting used on the MPC8360AMDS board with DDR2 SODIMM.
##############################################
# DDR Controller Configuration
##############################################
#DDRCDR
# hardware compensation, 75ohm, DRQ
writemem.l 0xE0000128 0x80000001
#CLK_CNTL
# bit 0 = 1 - SS_EN address and command sent to the DDR source synchronously
# bit 5-7 = 2 - CLK_ADJST
writemem.l 0xE0002130 0x02000000
# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002000 0x0000000f ; 256MB
# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns
writemem.l 0xe0002080 0x80440102
# TIMING_CFG_0
# RWT = b'00' ; 0 Clocks
# WRT = b'00' ; 0 Clocks
# RRT = b'00' ; 0 Clocks
# WWT = b'00' ; 0 Clocks
# ACT_PD_EXIT = b'010' ; 2 Clocks (txard=2tck)
# PRE_PD_EXIT = b'010' ; 2 Clocks (txp=2tck)
# ODT_PD_EXIT = b'1000' ; 8 Clocks (taxpd=8tck)
# MRS_CYC = b'0010' ; 2 Clocks (tmrd=2tck)
writemem.l 0xE0002104 0x00220802
# TIMING_CONFIG_1
# bit 1-3 - PRETOACT precharge activate interval 3 clock cycles
# bit 4-7 - ACTTOPRE activate to precharge interval 8 clock cycles
# bit 9-11 - ACTTORW activate to r/w interval 3 clock cycles
# bit 13 - 15 - CASLAT CAS latency 3 clock cycles
# bit 16 - 19 - REFREC refresh recovery time 7 clock cycles
# bit 21 - 23 - WRREC data to precharge interval 3 clock cycles
# bit 25 - 27 - ACTTOACT activate to activate interval 2 clock cycles
# bit 29 - 31 - 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l 0xe0002108 0x38357322
# TIMING_CONFIG_2
# ADD_LAT = b'010' ; 2 Clocks
# CPO = b'11111'
# WR_LAT = b'010' ; 2 Clocks
# RD_TO_PRE = b'010' ; 2 Clock (trtp=7.5ns)
# WR_DATA_DELAY = b'010' ; 1/2 Clocks
# CKE_PLS = b'011' ; 3 Clocks (tcke=3tck)
# FOUR_ACT = b'001000' ; 8 Clocks
writemem.l 0xe000210C 0x2f9048c8
# TIMING_CFG_3
# EXT_REFREC = b'000' ; 0 Clocks
writemem.l 0xE0002100 0x00000000
# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l 0xe0002110 0x43000000
# DDR_SDRAM_CFG_2
# assert ODT to IOs only during reads,1 refresh at a time
writemem.l 0xE0002114 0x00401000
# DDR_SDRAM_MODE
# bit 0 - 15 = 0x2000 - ESDMODE
# bit 16 - 31 = 0x0162 - SDMODE
writemem.l 0xe0002118 0x47d00432
# DDR_SDRAM_MODE_2
# Extended Mode Register 2
# Extended Mode Register 3
writemem.l 0xE000211C 0x8000c000
# DDR_SDRAM_INTERVAL
# bit 2 - 15 - REFINT
# bit 18 - 31 - BSTOPRE auto precharge r/w commands used
writemem.l 0xe0002124 0x05150080
#delay before enable
sleep 300
# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled
writemem.l 0xe0002110 0xc3000000
Regards,
Bulat
Thank you,
can you send config. for DDR1 with mpc8360e.
regards,
venkat.
This code was used on rev 1 silicon which did not support DDR2 at all. Should be functional also for rev 2.1 silicon with DDR1.
##############################################
# DDR Controllers Configuration
##############################################
# First DDR Controller Registers
#################################
#CLK_CNTL
# bit 0 = 1 - SS_EN address and command sent to the DDR source synchronously
# bit 5-7 = 2 - CLK_ADJST
writemem.l 0xE0002130 0x82000000
# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002000 0x00000007 ; 0x00000000 - 0x07FFFFFF # first 128MB
# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 9 columns
writemem.l 0xe0002080 0x80000101
# CS1_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002008 0x0008000f ; 0x08000000 - 0x0FFFFFFF # last 128MB
# CS1_CONFIG
# bit 0 = 1 - CS_1_EN CS1 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_1 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_1 9 columns
writemem.l 0xe0002084 0x80000101
# TIMING_CONFIG_1
# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles
# bit 4-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles
# bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles
# bit 13 - 15 = 4 - CASLAT CAS latency 2.5 clock cycles
# bit 16 - 19 = 3 - REFREC refresh recovery time 11 clock cycles
# bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 29 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l 0xe0002108 0x37343321
# TIMING_CONFIG_2
# bit 19-21 = b010 - WR_DATA_DELAY - 1/2 DRAM clock delay
writemem.l 0xe000210C 0x00000800
# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
# bit16 = 0 - 2T disabled
writemem.l 0xe0002110 0x42000000
# DDR_SDRAM_MODE
# bit 0 - 15 = 0x2000 - ESDMODE
# bit 16 - 31 = 0x0162 - SDMODE
writemem.l 0xe0002118 0x20000162
# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x45b0 - REFINT
# bit 18 - 31 = 0x0100 - BSTOPRE auto precharge r/w commands used
writemem.l 0xe0002124 0x045b0100
#delay before enable
sleep 300
# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled
# bit16 = 0 - 2T disabled
writemem.l 0xe0002110 0xc2000000