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MPC 8349 interfaced with 32/64 bits DDR2 bus width

Question asked by Dorian Chambon on Dec 5, 2019
Latest reply on Dec 9, 2019 by ufedor


For my project, I use MPC8349 processor. I would like to set DDR memory controller parameters.

The DDR2 bus width shall be configurable in 32 bits mode or in 64 bits mode without HW modification. In 64 bits mode, 5 DDR2 chips are used (4 chips + 1 ECC) in 32 bits mode 3 DDR2 chips are used (2 DDR2 chips + 1 ECC) but other chips unused still connected.



- Does everyone have a return of experience ?

- What hardware precautions should we take in case of DDR2 chips connected to processor but unused ?

- How the processor MPC8349 deals with 32 bits or 64 bits bus width (internal mask ?, other method ?...) ?

-It is necessary to disable DDR2 clocks for chips unused in 32 bits mode ?