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Missing Register Definitions for SRTC

Question asked by Andrew Kinmont on Dec 4, 2019
Latest reply on Dec 19, 2019 by Andrew Kinmont


We are planning on using the SRTC timer as a means of bringing the i.MX RT1064 processor in our application out of SNVS mode. When we look in the Reference Manual, there seems to be some definitions missing for the critical registers.

In particular, the LPSRTCMR and LPSRTCLR registers are referenced in the text (see section, but there are no definitions for these registers. Further, bit 0 in the LPCR register appears to be the SRTC enable bit, and bit1 in the same register appears to be the time alarm interrupt enable, but these are both listed as reserved in the Reference Manual.

There are details in the drivers in the SDK, just nothing in the Reference Manual.

Is this just a documentation issue (accidental omission from the Reference Manual), or is there a plan to remove the SRTC timer from the i.MX RT1064 in a future release of the silicon?

Thanks and best regards,