Oliver He


Discussion created by Oliver He on Dec 4, 2019
Latest reply on Dec 11, 2019 by jeremyzhou


we use the DMA Controller to fill the transmit buffer. The data should then be transmitted by FlexSPI/Hyperbus. The Configuration of FlexSPI contains a free running clock because we communicate with an FPGA.

Our device is a RT1051.


We need to transfer more than 128 Byte (TX FIFO size). Hence, we rely on multiple minor or major loop executions.

The LUT is configured similar to AN12239 ("How to Enable HyperRAM with i.MX RT").

If we increase the transmission speed to a certain level, we experince the following behavior:

  • the data transmission on data lines contains "breaks". It looks like the lines are not actively driven during this times
  • CS/SS stays asserted
  • Clock continues to run (as expected)
  • the breaks seem to correlate with the times when the DMA refills the TX buffer

We can measure this by using chipscope. The picture shown is a high speed transfer (160MHz DDR -> 320MB/s). 0x0c is the value if the lines are not driven.


Is there a possibility to configure the chip select line of FlexSPI to be deasserted when there is no transmit data available but the transfer is not finished yet?

Thanks in advance and best regards,