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Questionable line of code in the routine to enable data cache

Question asked by Mark Butcher on Nov 27, 2019
Latest reply on Nov 28, 2019 by Kerry Zhou

Hi All

 

Looking at the routine to enable data cache (__STATIC_INLINE void SCB_EnableDCache (void)) I find this line of code:

 

SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */

 

According to the comment it is selecting data cache but according to the ARM documentation it is selecting instruction cache:

 

 

Therefore is the code wrong or is the comment wrong?

 

Regards

 

Mark

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