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Problems with LPCOpen 2.10 on LPC1788/LPC4078 and LwIP

Question asked by Carlo Bramini on Nov 22, 2019
Latest reply on Dec 9, 2019 by Felipe García

Hello,

I tried to make working LPCOpen 2.10 with some boards based on LPC1788 and LPC4078, but I got many troubles with networking and LwIP.

Actually, the first malfunction was the inability to detect link status.

After long debugging, I have identified some suspicious code, so I would be pleasured to know your opinion.

 

Inside  lpc_chip_177x_8x\src\enet_17xx_40xx.c there is this declaration:

 

/* Divider index values for the MII PHY clock */
STATIC const uint8_t EnetClkDiv[] = {4, 6, 8, 10, 14, 20, 28, 36, 40, 44,
                                     48, 52, 56, 60, 64};

 

However, the register MAC_MCFG is described inside UM10470 in this way:

 

Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported
Host Clock divided by 4 0 0 0 x 10
Host Clock divided by 6 0 0 1 0 15
Host Clock divided by 8 0 0 1 1 20
Host Clock divided by 10 0 1 0 0 25
Host Clock divided by 14 0 1 0 1 35
Host Clock divided by 20 0 1 1 0 50
Host Clock divided by 28 0 1 1 1 70
Host Clock divided by 36 1 0 0 0 80 [1]
Host Clock divided by 40 1 0 0 1 90 [1]
Host Clock divided by 44 1 0 1 0 100 [1]
Host Clock divided by 48 1 0 1 1 120 [1]
Host Clock divided by 52 1 1 0 0 130 [1]
Host Clock divided by 56 1 1 0 1 140 [1]
Host Clock divided by 60 1 1 1 0 150 [1]
Host Clock divided by 64 1 1 1 1 160 [1]

 

So, the table seems wrong because 00000 and 00001 both divided by 4, and this shifted everything by one position.

After correcting the code to:

 

/

* Divider index values for the MII PHY clock */
STATIC const uint8_t EnetClkDiv[] = {4, 4, 6, 8, 10, 14, 20, 28, 36, 40, 44,
                                     48, 52, 56, 60, 64};

 

I finally got correct frequency from MDC pin.

 

Next, it happened that the driver was unable to read from MDIO pin.

The writes happened successfully, but the reads didn't.

I discovered that because the samples were unable to detect when the cable was extracted or inserted.

After many hours of tries, I think that I discovered how to make it working.

From the UM10470, the P1[16 to 17] are assigned to a "Type W IOCON register" and actually it clearly states that bit 7 must be set to 1 for normal operation.

Inside lpc_board_ea_devkit_1788\src\board_sysinit.c, there is this code:

 

    {0x1, 16, (IOCON_FUNC1 | IOCON_MODE_INACT)},
    {0x1, 17, (IOCON_FUNC1 | IOCON_MODE_INACT)},

 

But this is wrong because it does not set bit 7 to 1.

After changing to:

 

    {0x1, 16, (IOCON_FUNC1 | IOCON_MODE_INACT | 0x80)},
    {0x1, 17, (IOCON_FUNC1 | IOCON_MODE_INACT | 0x80)},

 

the access to the registers has been fixed.

 

What do you think about these changes?

 

At the corrent state, the samples using LwIP with raw API work fine.

Sadly, the samples using LwIP and FreeRTOS still do not work.

I really hope that somebody could give some advices for making working the LwIP samples with FreeRTOS, because at the moment and many hours of debugging I'm a bit out of idea.

 

Thank you very much for your time.

 

Sincerely.

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