HI , we use i.mx8m to turn on lcd panel with sn65dsi84. when we set pixel clock to lvds , and we will see error message.
How do we know that the pixel clock has support on i.mx8m ?
Thanks.
[ [0;32m OK [0m] Started Serial Getty on ttymxc0.
[ 5.961159] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* Cannot setup PHY for mode: 1920x1080 @14350 kHz
[ 5.961165] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* PHY_REF clk: 27000000, bit clk: 86100000
[ [0;32m OK [0m] Started Getty on tty1.
[ [0;32m OK [0m] Reached target Login Prompts.
[ [0;32m OK [0m] Started Kernel Logging Service.
[ 6.056306] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* Cannot setup PHY for mode: 1920x1080 @14350 kHz
[ 6.056315] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* PHY_REF clk: 27000000, bit clk: 86100000
[ [0;32m OK [0m] Started Weston Wayland Compositor (on tty7).
[ 6.130920] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* Cannot setup PHY for mode: 1920x1080 @14350 kHz
[ 6.130926] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* PHY_REF clk: 27000000, bit clk: 86100000
[ [0;32m OK [0m] Reached target Multi-User System.
Starting Update UTMP about System Runlevel Changes...
[ [0;32m OK [0m] Created slice User Slice of root.
