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Set asrc input clock to SPDIF_RX_CLK on IMX6

Question asked by Manuel Bertran Alvarez on Nov 19, 2019
Latest reply on Nov 21, 2019 by Manuel Bertran Alvarez

Hi,

I am working on an audio application using an i.MX6ULL and I need to use the hardware ASRC of the processor with the S/PDIF RX clock on the asrc pair input.

The problem I have I that even after the S/PDIF dpll is locked I can't read the rate of the spdif_rx_clk so the pair configuration fails to calculate the input divisor.

In the reference manual I read that after the spdif dpll is locked the received rate is directly generated to spdif_rx_clk. Is that right or are there registers to configure to make it go through to the asrc controller?

 

Thank you,

Manuel BA

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