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CLRC663 EMD suppression (ISO14443)

Question asked by Tom Heckel on Nov 12, 2019
Latest reply on Jan 2, 2020 by Estephania Martinez



while working with the CLRC663 chip I came across the RxCtrl register and saw the EMD_Sup bit.


I pretty much understand the EMD behaviour in general.

But what I don't understand is how the chip can be SURE that the error which appeared in the first 3 bytes is EMD related?


I know that there is a minimum time definition in which the PICC is not allowed to create any disturbance before sending the response. But the time before that (in which the PICC is allowed to disturb the field) can be so much longer (Frame Waiting Time).


Can anyone explain this to me?


Thanks in advance.


Best regards, Tom