Connecting LS1020A SGMII to 1000BASE-X w/o PHY?

[rainer_boschung]

Hi

in our system we use 1000BASE-X (w/o electrical-to-optical converter, full duplex, fix rate, no AN) for on our backplane ethernet communication. For the design of a new module we selected the LS1020 as board controller, and we intent to connect it directly to the backplane w/o any PHY. We assume this should be feasible since the the SGMII and 1000BASE-X are compatible, as long as no speed adaptation is required. 

• Can you confirm that the #LS1020A in #SGMII mode can be connected to a 1000BASE-X w/o  PHY?
• Or must we use 1000BASE-KX? (but seems not to be supported by the LS1020A)
• Is there any special feature to be considered when configuring this application case?
• Could you provide any pointers to code examples U-Boot, Kernel DTS

Thanks

Rainer

[Pavel]

See the following pages about auto-negotiation:

Solved: 1000BASE-X PCS/PMA or SGMII core 1000BASE-X auto-n... - Community Forums 

communication - What is the exact difference between SGMII and 1000Base-X? - Electrical Engineering ... 

Have a great day,
Pavel Chubakov

[rainer_boschung]

After a lot of reading I increased my  confidence that a direct connection of the LS1020 to our 1000Base-X -backplane is feasible.

I think the following configuration could work. It configures the eTESC to operate in 1000BASE-X full-duplex mode without auto-neg. Can anybody confirm this?

MAC configuration:

• ECNTRL[TBIM]=1, ECNTRL[SGMIIM]=1, ECNTRL[R100M]=0
• MACCFG2[I/F Mode]=0b10

TBI configuration:

• CR[Speed_0, Speed_1]=0b01, CR[AN_Enale]=0, CR[Full_Duplex]=1
• ANA[Half-duplex]=0, ANA[Full-duplex]=1
• TBICON[AN_Sense]=1, TBICON[MII_Mode]=0

But since the ANLPBPA register cannot be written I do not see how the MAC gets knowledge of the link partner abilities. Could anybody help me with this topic.

Thanks
Rainer

[Pavel]

See the following page about problem for your connection:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

https://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf

Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[rainer_boschung]

Hi Pavel,

thanks for your support.

Intel's errata concerns implementation in their FPGAs only (I think). Since we will not connect to an Intel FPGA, I think this will not be an issue for us. We intend to connect the LS1021 SerDes pins running SGMII directly connected to a 1340 from Marvell.

Have a nice day,

Rainer