From the user's manual the default AHB_CLK_ROOT is 12MHz
but as far as I can work out this is, in default state after reset, derived from OSC_CLK (from bypassed PLL2-PFD3) with no dividers in the path. If I switch AHB_CLK_ROOT immediately to CCM_CLKO1 I also see 24MHz.
Also for IPG_CLK_ROOT and PERCLK_CLK_ROOT I see no indication o dividers by default and I also measure 24MHz for both.
Is this an error in the user's manual or is there another explanation?
24MHz suggests that it is connected to OSC_CLK by default but I measure 3MHz, which matches with the tree diagram with a fixed /8:
Also, in the user's manual all references to PLL-PFD3 are for 297MHz, although the register's default is the same as PFD1 (which would be 594MHz).
Looking at the clock config tool it shows 594Mz for PLL2-PFD3 (matching with the CCM_ANALOG_PFD_528 default state in the user's manual and also in the HW).
Is the user's manual at fault or is there a reason why it always reference 297MHz?
The more worrying question is whether the MAX limits as specified in the user's manual can be trusted? There are no such values in the chip's data sheet and so the only ones available are the ones in the user's manual table!!!