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i.MX 8M Mini eMMC Boot Fusing

Question asked by Marcel Ziswiler on Nov 8, 2019
Latest reply on Nov 13, 2019 by igorpadykov

Trying to get eMMC booting going on an i.MX 8M Mini based design I stumbled over several shortcomings of the current reference manual (IMX8MMRM Rev. 2, 08/2019) which require clarifying:

 

Table 6-3. GPIO override contact assignments

=> By contact you probably mean pin, right?

 

6.1.4.7 Persistent bits

Table 6-8. Persistent bits

=> Table talks about SRC_GPR10 bits 29 and 30 but 6.5.5.26 SRC General Purpose Register 10 (SRC_GPR10) shows everything as reserved.

 

Table 6-19. USDHC boot eFUSE descriptions

=> That table seems to be rather messed up:

Shipped value of 000 for single bit BOOT_CFG[7].

Missing settings for Bus width BOOT_CFG[6:4].

Rows 7 and 8 are completely messed up:

MMC Speed Mode (CFG[3:2])

USDHC1 IO Voltage Selection (CFG[1])

=> Fuse column talks about BOOT_CFG vs. 0x490 and 0x4A0 but unclear what exact fuses that now is.

=> Order of rows (e.g. starts with bit 7 down to bit 0 and then bit 15 down to 8) is very confusing.

 

6.1.5.4.2 MMC and eMMC boot

eMMC4.3 or eMMC4.4 device supporting special boot mode

The BOOT ACK is selected by the .

=> I guess there is something crucial missing before that dot.

eMMC4.4 device

This mode can be selected by the BOOT_CFG2[7:5] (bus width) fuse.

=> Can't find any further mentioning of that BOOT_CFG2[7:5] anywhere.

 

6.1.5.4.4 IOMUX configuration for SD/MMC

Table 6-22. SD/MMC IOMUX pin configuration

=> Is it really true that for USDHC1 and USDHC2 DATA4 to DATA7 are not using their native SD1 resp. SD2 pins but rather some weird ECSPI1 resp. ECSPI2 alt2 ones? Anyway, so far, trying 4-bit only mode also does not seem to work.

 

6.1.5.4.5 Redundant boot support for expansion device

=> It's not quite clear whether or not this section also applies to eMMC and more specifically its fast boot mode as well. E.g. do the same image offsets apply or are they different when putting stuff into the eMMC hardware boot area partitions?

 

6.2.1 Boot Fusemap

=> Confusing use of BOOT_CFG vs. 0x470.  I assume they mean the same thing.

 

Table 6-43. MMC/eMMC Boot Fusemap

=> Doe the "Power Cycle Enable" and/or "SD Loopback Clock Source SEL" settings actually really matter at all if booting from eMMC?

=> Row 0x470[7:0] mentions "Reserved for HS200". Is HS200 actually supported for eMMC booting at all?

 

6.3.2.2 Fuse Shadow Memory Footprint

=> That graphic show 5 BOOT_CFGs, however, it is not quite clear what exactly is meant by those.

 

6.3.4 OCOTP Memory Map/Register Definition

OCOTP memory map

=> At least here there is the first concrete mentioning if OTP banks and words but what exactly they map to now is still not quite clear e.g.

Value of OTP Bank1 Word3 (Boot Configuration Info.) (OCOTP_HW_OCOTP_BOOT_CFG0)

Value of OTP Bank2 Word0 (Boot Configuration Info.) (OCOTP_HW_OCOTP_BOOT_CFG1)

Value of OTP Bank2 Word1 (Boot Configuration Info.) (OCOTP_HW_OCOTP_BOOT_CFG2)

Value of OTP Bank2 Word2 (Boot Configuration Info.) (OCOTP_HW_OCOTP_BOOT_CFG3)

Value of OTP Bank2 Word3 (BOOT Configuration Info.) (OCOTP_HW_OCOTP_BOOT_CFG4)

 

Could you please clarify the above items or at least give us a clear understanding of how exactly e.g. the imx8mm_evk could be fused to boot from its eMMC?

 

Anyway, our current fusing looks as follows but that does not quite seem to work as of yet:

fuse prog 1 3 0x100020d6 (BT_FUSE_SEL, eMMC boot, SD1, fast boot, 4-bit DDR, high speed, 1.8V)
fuse prog 2 2 0x00000001 (enable boot ack)

 

And the matching eMMC configuration:

mmc bootbus 0 1 0 2 (4-bit, reset bus width, DDR)
mmc partconf 0 1 1 0 (booting from boot area partition 1, send acknowledge)

 

BTW: That imx8mm_evk does not seem to connect the eMMC's reset aka RST# signal. Is that really recommended and has no adverse effect even considering eMMC fast boot spec actually requiring it?

 

Thanks!

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