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KW36 - SPI - troubles with TX FIFO & bit shifting

Question asked by Loïc GUILLAUME on Nov 8, 2019
Latest reply on Nov 13, 2019 by Mario Ignacio Castaneda Lopez

Hello,

 

Some context here : I'm using a MKW36 on a custom shield plugged on a nucleo L053R8. The goal is to replicate the S2-LP behaviour as 2.4Ghz sniffer. 

 

I'm having issues to understand something that is happening while I'm using SPI. Please find attached my code (forked from nxp example).

 

after using DSPI_SlaveTransferNonBlocking(SPI1, &g_s_handle, &slaveXfer), the registers state is correct : 

 

 

SR & TX0 are as expected.

 

On the master side, i'm sending a byte (CS low). I want the slave to send 0xAA but it sends 0x00. And if repeat the operation with another transfer right after (sending 0xBB for example). 0xAA is sent. The CS didn't return to the higher state.

I cannot understand the "delay". 

 

Also if the CS go HIGH then LOW between the transfer, there is no "delay" but the first byte sent is still 0x00.

 

I would greatly appreciate if you have some indications for me.

 

Regards,

Loic

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