i.MXRT1060 SEMC, Where and What is "DQSE"?

[TomE]

I'm looking at "i.MX RT1060 Processor Reference Manual, Rev. 1" and also "i.MX RT1064 Processor Reference Manual, Rev. 0.1" in case it is different (it isn't).

Starting with "Figure 24-38. NAND Flash access command type - Command + Address + Read Phase" and continuing in another 20 diagrams for FLASH and SRAM access, there's a "DQSE" signal shown.

This signal is not mentioned at all in "24.3 Signals" or "24.5.3 Pin Mux in SEMC".

"24.3 Signals" also shows "DQS4" as "Data read strobe for NAND Flash". But there's no further mention of it in any of the timing diagrams. The NAND ones all show "dqse" and "DQS" and not "DQS4".

The Data Sheet "i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0" gives the signal timings. It documents "DQS", but not "dqse" or "DQS4".

Could you please detail the "dqse" signal and which pin on the CPU it is? Or what it is?

Tom

[fangfang]

hello,

Yes, Please refer to the thread https://community.nxp.com/message/1107229?commentID=1107229#comment-1107229 .

Hope it help you. Have a nice day.

[TomE]

I see this question has been asked before, here:

https://community.nxp.com/message/1107229?commentID=1107229#comment-1107229 

In that post the answer was:

> dqse is module internal signal doesn't output to external SRAM, which is also suitable with ipg_clk.

It is only confusing as there's nothing in the manual to say that, and the presence of "dqse" in the traces doesn't add anything useful to us.

Tom