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How to clear the System FIFO transmit

Question asked by Chris ONeill on Nov 5, 2019
Latest reply on Nov 7, 2019 by Alexis Andalon

Using the 54102 with the System FIFO connected to a SPI peripheral.  Each transaction leaves a few extra bytes in the transmit FIFO, want to clear before the next transaction.  Set the TXFLUSH bit in the CTLSETSPI register, then TXFLUSHCLR bit in CTLCLRSPI register.  TXCOUNT doesn't change and the extra bytes are transmitted out in the next SPI operation.

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