I'm using LS1021a micro and when I transfer data from QorIQ, in out signals I get the attached picture (yellow = clk, green = cs)
There is a large gap between bytes and it is not always the same.
I would like to reduce this gap to the minimum possible.
- SPIDEV library.
- C and Python code
- SPI mode 3.
- Clock Tested: 1MHz, 4MHz, 8MHz...
- Kernel 4.14.78.
Thank you in advance.
PD: Attached picture and source code used for test.