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LPC55S69 : Core0 and Core1 debug traces

Question asked by Eugene Hiihtaja on Nov 1, 2019
Latest reply on Nov 5, 2019 by ZhangJennie

Hello !

 

I think it is not possible to share HW efficiently between 2 Cores and I can see in examples you promote different UARTs for traces in case of multiple cores usage.

 

Can sharing be done by using Mutex mechanism what is used if need to update shared SRAM memory in case of Mailbox usage ?

 

Can SWO traces be used on Core1 ?

 

Is any other solution when one peripheral can be shared to both cores without waiting overhead  ?

 

Regards,

Eugene

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