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What hardware multiply option is implemented in the MKW41Z Cortex-M0+ core?

Question asked by Colin McCormack on Oct 31, 2019
Latest reply on Nov 4, 2019 by Felipe García

See this thread for background information Use of Cortex-M0/M0+ multiply instructions on LPC43xx and LPC5410x

The Cortex-M0 and Cortex-M0+ CPU cores can be implemented with one of two hardware multiply options:

 

      
  • Fast : This allows the MULS instruction to execute in a single cycle

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  • Small : An iterative multiplier that takes 32 cycles to execute a MULS instruction.

 

For most NXP MCU's which use these cores, the 'Fast' option is implemented. However I am unable to definitively determine what option the MKW41Z512VHT4 has. 

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