What hardware multiply option is implemented in the MKW41Z Cortex-M0+ core?

[colinmccormack]

See this thread for background information Use of Cortex-M0/M0+ multiply instructions on LPC43xx and LPC5410x

The Cortex-M0 and Cortex-M0+ CPU cores can be implemented with one of two hardware multiply options:

• Fast : This allows the MULS instruction to execute in a single cycle

• Small : An iterative multiplier that takes 32 cycles to execute a MULS instruction.

For most NXP MCU's which use these cores, the 'Fast' option is implemented. However I am unable to definitively determine what option the MKW41Z512VHT4 has. 

[FelipeGarcia]

Hi Colin,

KW41Z device implements single-cycle multiplier. Please have a look to the table below from reference manual (chapter 3.3.1.1).

I hope this helps.

Best regards,

Felipe

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------