I have IFC_TE strapped incorrectly for the location of the Boot flash. The board is designed to boot RCW/PBI from SPI and then load boot code from NOR flash on CS0. The NOR flash is on the fast side of the IFC subsystem. The transceiver is active when IFC_TE is low.
My problem is that if I pull IFC_TE low to make the T2080 operate as desired for NOR on the fast side, then the transceiver is enabled and will mess with the LAD lines providing the strapping (if IFC_BCTL is also low). Thus I seem to be stuck in a bad spot.
Can you tell me (I will verify in the lab shortly) if IFC_BCTL is high or lower during PORESET assertion?
I was thinking I could leave IFC_TE strapped high as I have it to leave the transceiver off and then use the PBL to change CSPR0[TE]. But that doesn't appear like it will work as at the end of PBL the T2080 will write over CSPR0 anyway and cancel whatever I would have changed. Is that correct - that any changes I make to CSPR0 will be wiped out when the PBL is done loading (even though it isn't loading PBL from NOR, but rather from SPI). (section 188.8.131.52 of T2080 Ref Man).