Cal LPC55S69 reboot to ISP mode itself ?
I mean ISP boot pin is set to Low state externally, Core0 execute System reset and via reboot it start to stay in Bootrom and wait update package.
Some SRAM memory can stay untouched ?
If Core1 code is executed from SRAM, it can continue execution after System Reset as well.
Some SRAM areas what is not used by Bootloader can keep their context as well.
Or after System reset only RTC registers is untouched ?
Or hoe to keep Core1 running while ISP update and have posibility to reboot to ISP and return back and keep Core1 running from SRAM at at the same time ?