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On Chip DDR3L interfacing challenges with T1024

Question asked by Krushang Gandhi on Oct 30, 2019
Latest reply on Nov 5, 2019 by ufedor

Hi NXP Team,

 

We want to design customized board for one of the our project based on T1024 microprocessor and we want to use 4 on board DDR3L memory chips as per below details. We have tried to refer schematic of the development board schematic as available on the Product page of T1024 microprocessor. However in that, off board DDR3 module has been used by using UDIMM connector in which all the signals coming from T1024 has been used.

 

DDR3L Memory part details:

MFG No. : MT41K128M16JT-107 IT:K

Manufacturer: Micron Technology

Configuration: 16 Meg x 16 x 8 banks

 

We have below listed queries while designing schematic using above DDR3L part with T1024.

 

1) As per T1024 pinout, two differential clock output signals (MCK0 and MCK1) are there. For 4 discrete DDR3L memory chips, we should connect MCK0 output to all the four chips or MCK0 output to 2 memory ICs and MCK1 to the other two chips. Please confirm.

 

2) Please confirm CLK and CLKn termination techniques as per below reference image or suggest any other better suggestions if any.

 

 

3) Please suggest a method to connect termination decaps for each of the address or control signals i.e. 0.1 uF capacitors should be connected to 1V35 of DDR to GND(as per Method -b in the image) or it should be connected between VTT and 1V35(as per Method -b in the image).

 

Termination De-caps Methods:

 

4) In our case, we are not using error correcting algorithms for DDR3L. so,we should keep  D1_MECC[0..7] signals as NC or it has to be terminated with some proper method if any. Please suggest.

 

5) Regarding DDR reset signal, as per input of T1024 we did not find specific output pins from the T1024 processor. We have gone through the development board schematic for same and found that it has been connected from the output of the CPLD. However in our case, we have not used CPLD. So, please suggest from which output pin of T1024 DDR_reset needs to be connected? Or else, just power on reset with the processor would work ? Please suggest.

 

Please look in to above queries are share your inputs. In case of any query or further information is required please let me know.

 

Regards,

Krushang Gandhi

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