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LPC55S66 : flash memory banks ?

Question asked by Eugene Hiihtaja on Oct 29, 2019
Latest reply on Oct 29, 2019 by Alice_Yang

Hello !


Does  Core1 is not able to run from Flash memory in any case  or only if Core0 is not use it ?


In almost all SDK examples, Core 1 code is executed from RAM only.


So Flash memory is monolithic and not banked . It also mean that write/erase operation is stall execution of Core0 ?

But all flash API are located in ROM and it is not visible how all interrupts are enabled and disabled.


Could you clarify Flash memory behaviour in case of sharing it between Core0&1 and write/erase operations.